Analog Devices AD9912 specifications INPUT/OUTPUT Termination Recommendations

Page 15

AD9912

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

	0.01µF
AD9912		DOWNSTREAM
1.8V	100Ω	DEVICE
HSTL	100Ω	DEVICE
HSTL		(HIGH-Z)
OUTPUT		(HIGH-Z)
OUTPUT	0.01µF
	0.01µF

06763-027

0.1µF

CLOCK

SOURCE

WITH DIFF.100Ω OUTPUT

0.1µF

AD9912

SELF-BIASING

SYSCLK

INPUT

06763-030

Figure 33. AC-Coupled HSTL Output Driver

Figure 36. SYSCLK Differential Input, Non-Xtal

AD9912	50Ω
AD9912		DOWNSTREAM
1.8V		DEVICE
HSTL	AVDD/2	DEVICE
HSTL	AVDD/2	(HIGH-Z)
OUTPUT
	50Ω

06763-028

0.01µF

CLOCK SOURCE

WITH

SINGLE-ENDED

1.8V CMOS

OUTPUT0.01µF

AD9912

SELF-BIASING

SYSCLK

INPUT

06763-049

Figure 34. DC-Coupled HSTL Output Driver

10pF*

Figure 37. SYSCLK Single-Ended Input, Non-Xtal

AD9912

SELF-BIASING

SYSCLK

INPUT

10pF*

(CRYSTAL

MODE)

-029

*REFER TO CRYSTAL

06763

DATA SHEET.

0.1µF

100Ω (OPTIONAL)

0.1µF

AD9912

SELF-BIASING FDBK INPUT

06763-050

Figure 35. SYSCLK Input, Xtal

Figure 38. FDBK_IN Input

Rev. D Page 15 of 40

Image 15

Contents General Description FeaturesBasic Block Diagram ApplicationsTable of Contents Specifications DC SpecificationsParameter Min Typ Max Unit Test Conditions/Comments Total Power Dissipation System Clock InputClock Output Drivers Parameter Min Typ Max Unit Test Conditions/Comments AC SpecificationsAvss − Parameter Rating Absolute Maximum RatingsThermal Resistance ESD CautionInput Pin No Output Pin Type Mnemonic Description PIN Configuration and Function DescriptionsOutb ResetIoupdate GND AvssVideo BW Typical Performance CharacteristicsAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Theory of Operation OverviewDirect Digital Synthesizer DDS 1024  DIGITAL-TO-ANALOG DAC OutputReconstruction Filter Solving this equation for FTW yieldsDAC Spectrum vs. Reconstruction Filter Response Fdbkin InputsSysclk Inputs Functional DescriptionSysclk PLL Doubler External Loop Filter Sysclk PLL Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core Detail of Sysclk Differential InputsHarmonic Spur Reduction Output Clock Drivers and 2× Frequency MultiplierSpur Reduction Circuit Diagram Thermal Parameters Thermal PerformancePOWER-UP POWER-ON ResetDefault Output Frequency on POWER-UP Supplies Power Supply PartitioningSerial Control Port Serial Control Port PIN DescriptionsOperation of Serial Control Port Operations are changed to LSB first order MSB/LSB First TransfersInstruction Word 16 Bits ReadI15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB FirstParameter Description PLL Register MAPHSR-A Register Descriptions Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Power-up default is defined by the start-up pinsRegister 0x0021-Reserved Register 0x0022-PLL Parameters Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0020-N-DividerRegister 0x0106-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0105-S-DividerRegister 0x01AC-Phase Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AB-FTW0 Frequency Tuning WordRegister 0x040D to Register 0x0410-Reserved Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040C-DAC Full-Scale CurrentRegister 0x0506-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0505-Spur BOutline Dimensions AD9912BCPZ-REEL71 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ1Rev. D Page 40