Analog Devices AD9912 DC Specifications, Parameter Min Typ Max Unit Test Conditions/Comments

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AD9912

SPECIFICATIONS

DC SPECIFICATIONS

AVDD = 1.8 V ± 5%, AVDD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, AVSS = 0 V, DVSS = 0 V, unless otherwise noted.

Table 1.

Parameter	Min	Typ	Max	Unit	Test Conditions/Comments

SUPPLY VOLTAGE
DVDD_I/O (Pin 1)	3.135	3.30	3.465	V
DVDD (Pin 3, Pin 5, Pin 7)	1.71	1.80	1.89	V
AVDD3 (Pin 14, Pin 46, Pin 47, Pin 49)	3.135	3.30	3.465	V
AVDD3 (Pin 37)	1.71	3.30	3.465	V	Pin 37 is typically 3.3 V but can be set to 1.8 V
AVDD (Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29,	1.71	1.80	1.89	V
Pin 30, Pin 36, Pin 42, Pin 44, Pin 45, Pin 53)
SUPPLY CURRENT					See also the Total Power Dissipation
					specifications
IAVDD3 (Pin 37)		8	9.6	mA	CMOS output driver at 3.3 V, 50 MHz, with
					5 pF load
IAVDD3 (Pin 46, Pin 47, Pin 49)		26	31	mA	DAC output current source, fS = 1 GSPS
IAVDD (Pin 11, Pin 19, Pin 23 to Pin 26, Pin 29,		113	136	mA	Aggregate analog supply, with system
Pin 30, Pin 36, Pin 42, Pin 44, Pin 45)					clock PLL, HSTL output driver, and S-divider
					enabled
IAVDD (Pin 53)		40	48	mA	DAC power supply
IDVDD (Pin 3, Pin 5, Pin 7)		205	246	mA	Digital core (SpurKiller off)
IDVDD_I/O (Pin 1, Pin 141)		2	3	mA	Digital I/O (varies dynamically)
LOGIC INPUTS (Except Pin 32)					Pin 9, Pin 10, Pin 54, Pin 55, Pin 58 to Pin 61,
					Pin 63, Pin 64
Input High Voltage (VIH)	2.0		DVDD_I/O	V
Input Low Voltage (VIL)	DVSS		0.8	V
Input Current (IINH, IINL)		±60	±200	µA	At VIN = 0 V and VIN = DVDD_I/O
Maximum Input Capacitance (CIN)		3		pF
CLKMODESEL (Pin 32) LOGIC INPUT					Pin 32 only
Input High Voltage (VIH)	1.4		AVDD	V
Input Low Voltage (VIL)	AVSS		0.4	V
Input Current (IINH, IINL)		−18	−50	µA	At VIN = 0 V and VIN = AVDD
Maximum Input Capacitance (CIN)		3		pF
LOGIC OUTPUTS					Pin 62 and the following bidirectional pins:
					Pin 9, Pin 10, Pin 54, Pin 55, Pin 63
Output High Voltage (VOH)	2.7		DVDD_I/O	V	IOH = 1 mA
Output Low Voltage (VOL)	DVSS		0.4	V	IOL = 1 mA
FDBK_IN INPUT					Pin 40, Pin 41
Input Capacitance		3		pF
Input Resistance	18	22	26	kΩ	Differential
Differential Input Voltage Swing	225			mV p-p	Equivalent to 112.5 mV swing on each leg;
					must be ac-coupled

Rev. D Page 3 of 40

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Contents General Description FeaturesBasic Block Diagram ApplicationsTable of Contents Specifications DC SpecificationsParameter Min Typ Max Unit Test Conditions/Comments Total Power Dissipation System Clock InputClock Output Drivers Parameter Min Typ Max Unit Test Conditions/Comments AC SpecificationsAvss − Parameter Rating Absolute Maximum RatingsThermal Resistance ESD CautionInput Pin No Output Pin Type Mnemonic Description PIN Configuration and Function DescriptionsOutb ResetIoupdate GND AvssVideo BW Typical Performance CharacteristicsAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Theory of Operation OverviewDirect Digital Synthesizer DDS 1024  DIGITAL-TO-ANALOG DAC OutputReconstruction Filter Solving this equation for FTW yieldsDAC Spectrum vs. Reconstruction Filter Response Fdbkin InputsSysclk Inputs Functional DescriptionSysclk PLL Doubler External Loop Filter Sysclk PLL Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core Detail of Sysclk Differential InputsHarmonic Spur Reduction Output Clock Drivers and 2× Frequency MultiplierSpur Reduction Circuit Diagram Thermal Parameters Thermal PerformancePOWER-UP POWER-ON ResetDefault Output Frequency on POWER-UP Supplies Power Supply PartitioningSerial Control Port Serial Control Port PIN DescriptionsOperation of Serial Control Port Operations are changed to LSB first order MSB/LSB First TransfersInstruction Word 16 Bits ReadI15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB FirstParameter Description PLL Register MAPHSR-A Register Descriptions Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Power-up default is defined by the start-up pinsRegister 0x0021-Reserved Register 0x0022-PLL Parameters Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0020-N-DividerRegister 0x0106-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0105-S-DividerRegister 0x01AC-Phase Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AB-FTW0 Frequency Tuning WordRegister 0x040D to Register 0x0410-Reserved Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040C-DAC Full-Scale CurrentRegister 0x0506-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0505-Spur BOutline Dimensions AD9912BCPZ-REEL71 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ1Rev. D Page 40