Analog Devices AD9912 specifications DDS Run at 200 Msps for 10 MHz Plot

Page 12

AD9912

 

–100

(dBc/Hz)NOISE

–110

–120

 

PHASE

–130

 

 

–140

 

–150

 

100

RMS JITTER (100Hz TO 100MHz): 600MHz: 585fs

800MHz: 406fs

800MHz

600MHz

1k

10k

100k

1M

10M

100M

FREQUENCY OFFSET (Hz)

06763-015

 

800

 

 

 

 

 

 

 

 

 

TOTAL

 

 

 

 

 

 

700

3.3V

 

 

 

 

 

 

 

1.8V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(mW)

600

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DISSIPATION

500

 

 

 

 

 

 

 

400

 

 

 

 

 

 

 

300

 

 

 

 

 

 

 

POWER

 

 

 

 

 

 

 

200

 

 

 

 

 

 

 

 

100

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

-018

 

250

375

500

625

750

875

1000

 

06763

 

 

 

SYSTEM CLOCK FREQUENCY (MHz)

 

 

Figure 15. Absolute Phase Noise Using HSTL Driver,

SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed),

HSTL Output Doubler Enabled

 

–110

 

 

RMS JITTER (100Hz TO 20MHz):

 

 

 

 

 

 

 

 

 

 

150MHz: 308fs

 

 

 

 

–120

 

 

50MHz:

737fs

 

 

 

(dBc/Hz)NOISE

 

 

 

 

 

 

 

–130

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PHASE

–140

 

 

 

 

 

 

 

 

 

 

 

 

150MHz

 

 

 

–150

 

 

 

 

50MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10MHz

 

 

 

–160

 

 

 

 

 

 

-016

 

100

1k

10k

100k

1M

10M

100M

 

06763

 

 

 

FREQUENCY OFFSET (Hz)

 

 

Figure 16. Absolute Phase Noise Using CMOS Driver at 3.3 V, SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)

DDS Run at 200 MSPS for 10 MHz Plot

Figure 18. Power Dissipation vs. System Clock Frequency

(SYSCLK PLL Bypassed), fOUT = fSYSCLK/5, HSTL Driver On, CMOS Driver On,

SpurKiller Off

 

800

 

 

 

 

 

 

700

 

 

 

 

 

(mW)

600

 

 

 

 

 

 

 

 

 

 

 

DISSIPATION

500

 

 

 

 

 

400

 

 

 

 

 

300

 

 

 

TOTAL

 

POWER

 

 

 

 

 

 

 

3.3V

 

 

 

 

 

 

 

 

 

 

1.8V

 

200

 

 

 

 

 

 

100

 

 

 

 

 

 

0

 

 

 

 

-019

 

0

100

200

300

400

 

06763

 

 

OUTPUT FREQUENCY (MHz)

 

Figure 19. Power Dissipation vs. Output Frequency

SYSCLK = 1 GHz (SYSCLK PLL Bypassed), HSTL Driver On,

CMOS Driver On, SpurKiller Off

 

–110

(dBc/Hz)NOISE

–120

–130

 

PHASE

–140

 

 

–150

 

–160

 

100

RMS JITTER (100Hz TO 20MHz): 50MHz: 790fs

 

 

 

 

50MHz

 

 

 

 

 

10MHz

 

1k

10k

100k

1M

10M

100M

 

FREQUENCY OFFSET (Hz)

 

 

06763-017

 

10

CARRIER:

 

 

 

 

 

 

0

 

399MHz

 

 

 

 

SFDR W/O SPURKILLER:

–63.7dBc

 

 

 

 

–10

SFDR WITH SPURKILLER: –69.3dBc

 

 

 

 

FREQUENCY SPAN:

500MHz

 

 

 

 

 

 

 

 

(dBm)

–20

RESOLUTION BW:

3kHz

 

 

 

VIDEO BW:

 

30kHz

 

 

 

 

 

 

 

 

–30

 

THESE TWO SPURS

 

 

 

POWER

–50

 

 

 

 

 

–40

 

 

 

 

 

 

SIGNAL

 

 

ELIMINATED WITH

 

 

 

–60

 

SPURKILLER

 

 

 

 

 

 

 

 

 

–70

 

 

 

 

 

 

 

–80

 

 

 

 

 

 

 

–90

 

 

 

 

 

 

 

–100

 

 

 

 

 

-020

 

0

100

200

300

400

500

 

06763

 

 

 

FREQUENCY (MHz)

 

 

Figure 17. Absolute Phase Noise Using CMOS Driver at 1.8 V, SYSCLK = 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)

Figure 20. SFDR Comparison With and Without SpurKiller,

SYSCLK = 1 GHz, fOUT = 400 MHz

Rev. D Page 12 of 40

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Contents Features Basic Block DiagramApplications General DescriptionTable of Contents Specifications DC SpecificationsParameter Min Typ Max Unit Test Conditions/Comments Total Power Dissipation System Clock InputClock Output Drivers AC Specifications Parameter Min Typ Max Unit Test Conditions/CommentsAvss − Absolute Maximum Ratings Thermal ResistanceESD Caution Parameter RatingPIN Configuration and Function Descriptions Input Pin No Output Pin Type Mnemonic DescriptionReset IoupdateGND Avss OutbTypical Performance Characteristics Video BWAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Theory of Operation OverviewDirect Digital Synthesizer DDS DIGITAL-TO-ANALOG DAC Output Reconstruction FilterSolving this equation for FTW yields 1024 Fdbkin Inputs DAC Spectrum vs. Reconstruction Filter ResponseSysclk Inputs Functional DescriptionSysclk PLL Doubler Sysclk PLL Multiplier Sysclk PLL multiplier has a 1 GHz VCO at its coreDetail of Sysclk Differential Inputs External Loop Filter Sysclk PLLOutput Clock Drivers and 2× Frequency Multiplier Harmonic Spur ReductionSpur Reduction Circuit Diagram Thermal Performance Thermal ParametersPOWER-UP POWER-ON ResetDefault Output Frequency on POWER-UP Power Supply Partitioning SuppliesSerial Control Port Serial Control Port PIN DescriptionsOperation of Serial Control Port MSB/LSB First Transfers Instruction Word 16 BitsRead Operations are changed to LSB first orderSerial Control Port, 16-Bit Instruction Word, MSB First I15 I14 I13 I12 I11 I10 A12 A11 A10Parameter Description Register MAP PLLHSR-A Register 0x0000-Serial Port Configuration Register 0x0010-Power-Down and EnablePower-up default is defined by the start-up pins Register DescriptionsRegister 0x0011-Reserved Register 0x0012-Reset Autoclearing Register 0x0013-Reset Not AutoclearingRegister 0x0020-N-Divider Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x01A7-FTW0 Frequency Tuning Word Register 0x01A8-FTW0 Frequency Tuning WordRegister 0x0105-S-Divider Register 0x0106-S-DividerRegister 0x01A9-FTW0 Frequency Tuning Word Register 0x01AA-FTW0 Frequency Tuning WordRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x0200-HSTL Driver Register 0x0201-CMOS DriverRegister 0x040C-DAC Full-Scale Current Register 0x040D to Register 0x0410-ReservedRegister 0x0503-Spur a Register 0x0504-Spur aRegister 0x0505-Spur B Register 0x0506-Spur BOutline Dimensions Model Temperature Range Package Description Package Option Ordering GuideAD9912BCPZ1 AD9912BCPZ-REEL71Rev. D Page 40