Analog Devices AD9912 specifications Outline Dimensions

Page 38

AD9912

OUTLINE DIMENSIONS

9.00

BSC SQ

PIN 1

INDICATOR

TOP

VIEW

	1.00	12° MAX	0.80 MAX
	1.00	12° MAX	0.65 TYP
	0.85		0.65 TYP
	0.85
	0.80
	SEATING		0.50 BSC
	PLANE

			0.30
		0.60 MAX	0.25
	0.60 MAX		0.18	PIN 1
			64	PIN 1
		4849	64	INDICATOR
		4849	1	INDICATOR
	8.75	EXPOSED PAD		*4.85
	BSC SQ	EXPOSED PAD		4.70 SQ
	BSC SQ	(BOTTOM VIEW)		4.70 SQ
		(BOTTOM VIEW)		4.55
				4.55
	0.50
	0.40	33	16
	0.30	32	17
			7.50
			REF
	0.05 MAX		FOR PROPER CONNECTION OF
	0.05 MAX		THE EXPOSED PAD, REFER TO
	0.02 NOM		THE PIN CONFIGURATION AND
			FUNCTION DESCRIPTIONS
	0.20 REF		SECTION OF THIS DATA SHEET.
	0.20 REF

*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

EXCEPT FOR EXPOSED PAD DIMENSION

082908-B

Figure 57. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-1)

Dimensions shown in millimeters

	9.10
	9.00 SQ				0.60 MAX
	8.90			0.60
				MAX			PIN 1
					4849	64 1	INDICATOR
PIN 1
INDICATOR
			8.85	0.50	EXPOSED		5.36
			8.75 SQ	BSC	PAD		5.21 SQ
			8.65				5.06
				0.50
				0.40	3332	17 16
				0.30	BOTTOM VIEW		0.25 MIN
	TOP VIEW						0.25 MIN
	TOP VIEW
1.00	12° MAX		0.80 MAX		7.50 REF
	12° MAX		0.80 MAX
			0.65 TYP			FOR PROPER CONNECTION OF
0.85			0.65 TYP			FOR PROPER CONNECTION OF
0.85			0.05 MAX			THE EXPOSED PAD, REFER TO
0.80			0.05 MAX			THE EXPOSED PAD, REFER TO
0.80			0.02 NOM			THE PIN CONFIGURATION AND
			0.02 NOM			FUNCTION DESCRIPTIONS
SEATING		0.30	0.20 REF			SECTION OF THIS DATA SHEET.
PLANE		0.23	0.20 REF
PLANE		0.23
		0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 58. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-7)

Dimensions shown in millimeters

062209-A

Rev. D Page 38 of 40

Image 38

Contents Applications FeaturesBasic Block Diagram General DescriptionTable of Contents Parameter Min Typ Max Unit Test Conditions/Comments SpecificationsDC Specifications Clock Output Drivers Total Power DissipationSystem Clock Input AC Specifications Parameter Min Typ Max Unit Test Conditions/CommentsAvss − ESD Caution Absolute Maximum RatingsThermal Resistance Parameter RatingPIN Configuration and Function Descriptions Input Pin No Output Pin Type Mnemonic DescriptionGND Avss ResetIoupdate OutbTypical Performance Characteristics Video BWAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Direct Digital Synthesizer DDS Theory of OperationOverview Solving this equation for FTW yields DIGITAL-TO-ANALOG DAC OutputReconstruction Filter 1024 Fdbkin Inputs DAC Spectrum vs. Reconstruction Filter ResponseSysclk PLL Doubler Sysclk InputsFunctional Description Detail of Sysclk Differential Inputs Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core External Loop Filter Sysclk PLLOutput Clock Drivers and 2× Frequency Multiplier Harmonic Spur ReductionSpur Reduction Circuit Diagram Thermal Performance Thermal ParametersDefault Output Frequency on POWER-UP POWER-UPPOWER-ON Reset Power Supply Partitioning SuppliesOperation of Serial Control Port Serial Control PortSerial Control Port PIN Descriptions Read MSB/LSB First TransfersInstruction Word 16 Bits Operations are changed to LSB first orderSerial Control Port, 16-Bit Instruction Word, MSB First I15 I14 I13 I12 I11 I10 A12 A11 A10Parameter Description Register MAP PLLHSR-A Power-up default is defined by the start-up pins Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Register DescriptionsRegister 0x0020-N-Divider Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x0105-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0106-S-DividerRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x040C-DAC Full-Scale Current Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040D to Register 0x0410-ReservedRegister 0x0505-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0506-Spur BOutline Dimensions AD9912BCPZ1 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ-REEL71Rev. D Page 40