Analog Devices AD9912 specifications Theory of Operation, Overview, Direct Digital Synthesizer DDS

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AD9912

THEORY OF OPERATION

 

 

 

 

OUT_CMOS

 

 

 

 

 

OUT

 

 

 

 

2×

OUTB

 

 

÷S

 

 

FDBK_IN

 

 

 

 

 

 

 

 

 

 

FDBK_INB

 

DIGITAL SYNTHESIS CORE

 

 

 

 

FREQUENCY

 

 

 

 

TUNING WORD

DAC_OUT

 

 

 

 

 

EXTERNAL

 

CONTROL

 

 

 

 

 

DDS/DAC

DAC_OUTB

ANALOG

 

LOGIC

 

LOW-PASS

 

 

 

 

 

 

 

 

FILTER

 

 

 

LOW NOISE

 

EXTERNAL

CONFIGURATION

 

CLOCK

 

LOOP

 

MULTIPLIER

 

FILTER

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

AMP

 

 

 

 

SYSCLK PORT

 

 

 

DIGITAL

 

 

 

-031

S1 TO S4

 

SYSCLK SYSCLKB

 

06763

 

INTERFACE

 

 

Figure 39. Detailed Block Diagram

OVERVIEW

The AD9912 is a high performance, low noise, 14-bit DDS clock synthesizer with integrated comparators for applications desiring an agile, finely tuned square or sinusoidal output signal. A digitally controlled oscillator (DCO) is implemented using a direct digital synthesizer (DDS) with an integrated output DAC, clocked by the system clock.

A bypassable PLL-based frequency multiplier is present, enabling use of an inexpensive, low frequency source for the system clock. For best jitter performance, the system clock PLL should be bypassed, and a low noise, high frequency system clock should be provided directly. Sampling theory sets an upper bound for the DDS output frequency at 50% of fS (where fS is the DAC sample rate), but a practical limitation of 40% of

fS is generally recommended to allow for the selectivity of the required off-chip reconstruction filter.

The output signal from the reconstruction filter can be fed back to the AD9912 to be processed through the output circuitry.

The output circuitry includes HSTL and CMOS output buffers, as well as a frequency doubler for applications that need frequencies above the Nyquist level of the DDS.

The AD9912 also offers preprogrammed frequency profiles that allow the user to generate frequencies without programming the part. The individual functional blocks are described in the following sections.

DIRECT DIGITAL SYNTHESIZER (DDS)

The frequency of the sinusoid generated by the DDS is determined by a frequency tuning word (FTW), which is a digital (that is, numeric) value. Unlike an analog sinusoidal generator, a DDS uses digital building blocks and operates as a sampled system. Thus, it requires a sampling clock (fS) that serves as the fundamental timing source of the DDS. The accumulator behaves as a modulo-248counter with a program- mable step size that is determined by the frequency tuning word (FTW). A block diagram of the DDS is shown in Figure 40.

Rev. D Page 16 of 40

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Contents Features Basic Block DiagramApplications General DescriptionTable of Contents DC Specifications SpecificationsParameter Min Typ Max Unit Test Conditions/Comments System Clock Input Total Power DissipationClock Output Drivers AC Specifications Parameter Min Typ Max Unit Test Conditions/CommentsAvss − Absolute Maximum Ratings Thermal ResistanceESD Caution Parameter RatingPIN Configuration and Function Descriptions Input Pin No Output Pin Type Mnemonic DescriptionReset IoupdateGND Avss OutbTypical Performance Characteristics Video BWAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Overview Theory of OperationDirect Digital Synthesizer DDS DIGITAL-TO-ANALOG DAC Output Reconstruction FilterSolving this equation for FTW yields 1024 Fdbkin Inputs DAC Spectrum vs. Reconstruction Filter ResponseFunctional Description Sysclk InputsSysclk PLL Doubler Sysclk PLL Multiplier Sysclk PLL multiplier has a 1 GHz VCO at its coreDetail of Sysclk Differential Inputs External Loop Filter Sysclk PLLOutput Clock Drivers and 2× Frequency Multiplier Harmonic Spur ReductionSpur Reduction Circuit Diagram Thermal Performance Thermal ParametersPOWER-ON Reset POWER-UPDefault Output Frequency on POWER-UP Power Supply Partitioning SuppliesSerial Control Port PIN Descriptions Serial Control PortOperation of Serial Control Port MSB/LSB First Transfers Instruction Word 16 BitsRead Operations are changed to LSB first orderSerial Control Port, 16-Bit Instruction Word, MSB First I15 I14 I13 I12 I11 I10 A12 A11 A10Parameter Description Register MAP PLLHSR-A Register 0x0000-Serial Port Configuration Register 0x0010-Power-Down and EnablePower-up default is defined by the start-up pins Register DescriptionsRegister 0x0011-Reserved Register 0x0012-Reset Autoclearing Register 0x0013-Reset Not AutoclearingRegister 0x0020-N-Divider Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x01A7-FTW0 Frequency Tuning Word Register 0x01A8-FTW0 Frequency Tuning WordRegister 0x0105-S-Divider Register 0x0106-S-DividerRegister 0x01A9-FTW0 Frequency Tuning Word Register 0x01AA-FTW0 Frequency Tuning WordRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x0200-HSTL Driver Register 0x0201-CMOS DriverRegister 0x040C-DAC Full-Scale Current Register 0x040D to Register 0x0410-ReservedRegister 0x0503-Spur a Register 0x0504-Spur aRegister 0x0505-Spur B Register 0x0506-Spur BOutline Dimensions Model Temperature Range Package Description Package Option Ordering GuideAD9912BCPZ1 AD9912BCPZ-REEL71Rev. D Page 40
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