Analog Devices AD9912 specifications Sysclk Inputs, Functional Description, Sysclk PLL Doubler

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AD9912

SYSCLK INPUTS

Functional Description

An external time base connects to the AD9912 at the SYSCLK pins to generate the internal high frequency system clock (fS).

The SYSCLK inputs can be operated in one of the following three modes:

SYSCLK PLL bypassed

SYSCLK PLL enabled with input signal generated externally

Crystal resonator with SYSCLK PLL enabled

A functional diagram of the system clock generator is shown in Figure 44.

The SYSCLK PLL multiplier path is enabled by a Logic 0 (default) in the PD SYSCLK PLL bit (Register 0x0010, Bit 4) of the I/O register map. The SYSCLK PLL multiplier can be driven from the SYSCLK input pins by one of two means, depending on the logic level applied to the 1.8 V CMOS CLKMODESEL pin. When CLKMODESEL = 0, a crystal can be connected directly across the SYSCLK pins. When CLKMODESEL = 1, the maintaining amp is disabled, and an external frequency source (such as an oscillator or signal generator) can be connected directly to the SYSCLK input pins. Note that CLKMODESEL = 1 does not disable the system clock PLL.

The maintaining amp on the AD9912 SYSCLK pins is intended for 25 MHz, 3.2 mm × 2.5 mm AT cut fundamental mode crystals with a maximum motional resistance of 100 Ω. The following crystals, listed in alphabetical order, meet these criteria (as of the revision date of this data sheet):

AVX/Kyocera CX3225SB

ECS ECX-32

Epson/Toyocom TSX-3225

Fox FX3225BS

NDK NX3225SA

Note that although these crystals meet the preceding criteria according to their data sheets, Analog Devices, Inc., does not guarantee their operation with the AD9912, nor does Analog Devices endorse one supplier of crystals over another.

When the SYSCLK PLL multiplier path is disabled, the AD9912 must be driven by a high frequency signal source (250 MHz to

1 GHz). The signal thus applied to the SYSCLK input pins becomes the internal DAC sampling clock (fS) after passing through an internal buffer.

It is important to note that when bypassing the system clock PLL, the LOOP_FILTER pin (Pin 31) should be pulled down to the analog ground with a 1 kΩ resistor.

SYSCLK PLL Doubler

The SYSCLK PLL multiplier path offers an optional SYSCLK PLL doubler. This block comes before the SYSCLK PLL multiplier and acts as a frequency doubler by generating a pulse on each edge of the SYSCLK input signal. The SYSCLK PLL multiplier locks to the falling edges of this regenerated signal.

The impetus for doubling the frequency at the input of the SYSCLK PLL multiplier is that an improvement in overall phase noise performance can be realized. The main drawback is that the doubler output is not a rectangular pulse with a constant duty cycle even for a perfectly symmetric SYSCLK input signal. This results in a subharmonic appearing at the same frequency as the SYSCLK input signal, and the magnitude of the subharmonic can be quite large. When employing the doubler, care must be taken to ensure that the loop bandwidth of the SYSCLK PLL multiplier adequately suppresses the subharmonic.

The benefit offered by the doubler depends on the magnitude of the subharmonic, the loop bandwidth of the SYSCLK PLL multiplier, and the overall phase noise requirements of the specific application. In many applications, the AD9912 clock output is applied to the input of another PLL, and the subhar- monic is often suppressed by the relatively narrow bandwidth of the downstream PLL.

Note that generally, the benefits of the SYSCLK PLL doubler are realized for SYSCLK input frequencies of 25 MHz and above.

 

PD SYSCLK PLL

 

 

 

BIPOLAR EDGE DETECTOR

 

 

 

 

 

(I/O REGISTER BIT)

 

 

(I/O REGISTER BIT)

 

 

 

 

 

 

 

SYSCLK PLL BYPASSED

 

 

 

 

 

 

 

SYSCLK

2

1 2

 

WITH EXTERNAL DRIVE

 

 

 

 

 

 

 

SYSCLKB

 

0 2

1

2

1

 

 

2

 

 

DAC

 

 

 

0

SYSCLK

1

2

 

 

SYSCLK

0 2

 

2

 

 

SAMPLE

 

 

0

1

PLL

0

 

CLOCK

 

 

PLL

 

 

 

MULTIPLIER

 

 

 

 

 

 

ENABLED

 

 

 

 

 

 

 

 

 

 

 

 

 

WITH CRYSTAL

 

BIPOLAR

 

 

 

 

 

 

 

 

 

 

EDGE

 

 

 

 

 

 

 

 

 

RESONATOR

 

 

 

 

 

 

CLKMODESEL

 

 

 

 

DETECTOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

06763-036

 

 

 

 

 

 

 

LOOP_FILTER

 

 

 

Figure 44. System Clock Generator Block Diagram

Rev. D Page 19 of 40

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Contents General Description FeaturesBasic Block Diagram ApplicationsTable of Contents DC Specifications SpecificationsParameter Min Typ Max Unit Test Conditions/Comments System Clock Input Total Power DissipationClock Output Drivers Parameter Min Typ Max Unit Test Conditions/Comments AC SpecificationsAvss − Parameter Rating Absolute Maximum RatingsThermal Resistance ESD CautionInput Pin No Output Pin Type Mnemonic Description PIN Configuration and Function DescriptionsOutb ResetIoupdate GND AvssVideo BW Typical Performance CharacteristicsAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Overview Theory of OperationDirect Digital Synthesizer DDS 1024  DIGITAL-TO-ANALOG DAC OutputReconstruction Filter Solving this equation for FTW yieldsDAC Spectrum vs. Reconstruction Filter Response Fdbkin InputsFunctional Description Sysclk InputsSysclk PLL Doubler External Loop Filter Sysclk PLL Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core Detail of Sysclk Differential InputsHarmonic Spur Reduction Output Clock Drivers and 2× Frequency MultiplierSpur Reduction Circuit Diagram Thermal Parameters Thermal PerformancePOWER-ON Reset POWER-UPDefault Output Frequency on POWER-UP Supplies Power Supply PartitioningSerial Control Port PIN Descriptions Serial Control PortOperation of Serial Control Port Operations are changed to LSB first order MSB/LSB First TransfersInstruction Word 16 Bits ReadI15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB FirstParameter Description PLL Register MAPHSR-A Register Descriptions Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Power-up default is defined by the start-up pinsRegister 0x0021-Reserved Register 0x0022-PLL Parameters Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0020-N-DividerRegister 0x0106-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0105-S-DividerRegister 0x01AC-Phase Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AB-FTW0 Frequency Tuning WordRegister 0x040D to Register 0x0410-Reserved Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040C-DAC Full-Scale CurrentRegister 0x0506-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0505-Spur BOutline Dimensions AD9912BCPZ-REEL71 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ1Rev. D Page 40