Analog Devices AD9912 specifications Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz

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AD9912

 

–115

 

 

RMS JITTER (100Hz TO 20MHz):

 

 

 

 

 

 

 

 

 

 

50MHz:

62fs

 

 

 

 

–125

 

 

200MHz:

37fs

 

 

 

 

 

 

400MHz: 31fs

 

 

 

 

 

 

 

 

 

 

(dBc/Hz)

–135

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOISE

–145

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PHASE

–155

 

 

 

 

400MHz

 

 

 

 

 

 

 

 

 

 

–165

 

 

 

200MHz

 

 

 

 

 

 

 

 

 

 

–175

 

 

 

50MHz

 

 

-051

 

 

 

 

 

 

 

 

100

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06763

 

 

 

FREQUENCY OFFSET (Hz)

 

 

 

–115

 

 

 

 

(dBc/Hz)

–125

 

 

–135

 

 

 

 

 

NOISE

–145

 

 

PHASE

–155

 

 

 

 

 

 

–165

 

 

 

–175

 

 

 

 

 

100

RMS JITTER (100Hz TO 100MHz): 83fs

1k

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100M

 

FREQUENCY OFFSET (Hz)

 

 

06763-054

Figure 21. Absolute Phase Noise of Unfiltered DAC Output, fOUT = 50 MHz, 200 MHz, and 400 MHz, SYSCLK Driven by a 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)

 

–115

 

 

RMS JITTER (100Hz TO 20MHz): 69fs

 

 

 

 

 

 

 

–125

 

 

 

 

 

 

 

(dBc/Hz)

–135

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOISE

–145

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PHASE

–155

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–165

 

 

 

 

 

 

 

 

–175

 

 

 

 

 

 

-052

 

100

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100k

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06763

 

 

 

FREQUENCY OFFSET (Hz)

 

 

Figure 22. Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz,

SYSCLK Driven by a 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)

 

–115

 

 

RMS JITTER (100Hz TO 40MHz): 61fs

 

 

 

 

 

 

 

–125

 

 

 

 

 

 

 

(dBc/Hz)

–135

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOISE

–145

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PHASE

–155

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–165

 

 

 

 

 

 

 

 

–175

 

 

 

 

 

 

-053

 

100

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1M

10M

100M

 

06763

 

 

 

FREQUENCY OFFSET (Hz)

 

 

Figure 23. Absolute Phase Noise of Unfiltered DAC Output, fOUT = 171 MHz,

SYSCLK Driven by a 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)

Figure 24. Absolute Phase Noise of Unfiltered DAC Output, fOUT = 258.3 MHz,

SYSCLK Driven by a 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)

 

–115

 

 

RMS JITTER (100Hz TO 100MHz): 82fs

 

 

 

 

 

 

 

–125

 

 

 

 

 

 

 

(dBc/Hz)

–135

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOISE

–145

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PHASE

–155

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–165

 

 

 

 

 

 

 

 

–175

 

 

 

 

 

 

-055

 

100

1k

10k

100k

1M

10M

100M

 

06763

 

 

 

FREQUENCY OFFSET (Hz)

 

 

Figure 25. Absolute Phase Noise of Unfiltered DAC Output, fOUT = 311.6 MHz,

SYSCLK Driven by a 1 GHz Wenzel Oscillator (SYSCLK PLL Bypassed)

 

–110

 

 

RMS JITTER (100Hz TO 100MHz): 22fs

 

 

 

 

 

 

 

–120

 

 

 

 

 

 

 

(dBc/Hz)

–130

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOISE

–140

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PHASE

–150

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

–160

 

 

 

 

 

 

 

 

–170

 

 

 

 

 

 

-056

 

100

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100M

 

06763

 

 

 

FREQUENCY OFFSET (Hz)

 

 

Figure 26. Absolute Phase Noise of 1 GHz Reference Used for Performance Plots; Wenzel Components Used: 100 MHz Oscillator, LNBA-13-24 Amp, LNOM 100-5 Multiplier, LNDD 500-14 Diode Doubler

Rev. D Page 13 of 40

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Contents Basic Block Diagram FeaturesApplications General DescriptionTable of Contents DC Specifications SpecificationsParameter Min Typ Max Unit Test Conditions/Comments System Clock Input Total Power DissipationClock Output Drivers Parameter Min Typ Max Unit Test Conditions/Comments AC SpecificationsAvss − Thermal Resistance Absolute Maximum RatingsESD Caution Parameter RatingInput Pin No Output Pin Type Mnemonic Description PIN Configuration and Function DescriptionsIoupdate ResetGND Avss OutbVideo BW Typical Performance CharacteristicsAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Overview Theory of OperationDirect Digital Synthesizer DDS Reconstruction Filter DIGITAL-TO-ANALOG DAC OutputSolving this equation for FTW yields 1024 DAC Spectrum vs. Reconstruction Filter Response Fdbkin InputsFunctional Description Sysclk InputsSysclk PLL Doubler Sysclk PLL multiplier has a 1 GHz VCO at its core Sysclk PLL MultiplierDetail of Sysclk Differential Inputs External Loop Filter Sysclk PLLHarmonic Spur Reduction Output Clock Drivers and 2× Frequency MultiplierSpur Reduction Circuit Diagram Thermal Parameters Thermal PerformancePOWER-ON Reset POWER-UPDefault Output Frequency on POWER-UP Supplies Power Supply PartitioningSerial Control Port PIN Descriptions Serial Control PortOperation of Serial Control Port Instruction Word 16 Bits MSB/LSB First TransfersRead Operations are changed to LSB first orderI15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB FirstParameter Description PLL Register MAPHSR-A Register 0x0010-Power-Down and Enable Register 0x0000-Serial Port ConfigurationPower-up default is defined by the start-up pins Register DescriptionsRegister 0x0013-Reset Not Autoclearing Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0020-N-Divider Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x0105-S-Divider Register 0x0106-S-DividerRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x0201-CMOS Driver Register 0x0200-HSTL DriverRegister 0x040C-DAC Full-Scale Current Register 0x040D to Register 0x0410-ReservedRegister 0x0504-Spur a Register 0x0503-Spur aRegister 0x0505-Spur B Register 0x0506-Spur BOutline Dimensions Ordering Guide Model Temperature Range Package Description Package OptionAD9912BCPZ1 AD9912BCPZ-REEL71Rev. D Page 40