AD9912
CSB
SCLK
SDIO
tS
tDS
tCLK
tHIGH
tDH
BIT N
tLOW
BIT N + 1
tH
Figure 56. Serial Control Port Timing—Write
Table 11. Definitions of Terms Used in Serial Control Port Timing Diagrams
Parameter | Description |
tCLK | Period of SCLK |
tDV | Read data valid time (time from falling edge of SCLK to valid data on SDIO/SDO) |
tDS | Setup time between data and rising edge of SCLK |
tDH | Hold time between data and rising edge of SCLK |
tS | Setup time between CSB and SCLK |
tH | Hold time between CSB and SCLK |
tHI | Minimum period that SCLK should be in a logic high state |
tLO | Minimum period that SCLK should be in a logic low state |
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