Analog Devices AD9912 specifications DIGITAL-TO-ANALOG DAC Output, Reconstruction Filter, 1024 

Page 17

AD9912

 

48-BIT ACCUMULATOR

 

PHASE

 

 

DAC I-SET

DAC_RSET

 

OFFSET

 

 

REGISTERS

 

 

 

 

48

 

 

 

 

AND LOGIC

 

 

 

 

 

14

 

 

 

 

FREQUENCY

48

48

D Q

19

19

ANGLE TO

14

DAC

DAC_OUT

TUNING WORD

 

 

 

 

AMPLITUDE

 

(14-BIT)

 

(FTW)

 

 

 

 

 

CONVERSION

 

DAC_OUTB

 

 

 

 

 

 

 

fS

Figure 40. DDS Block Diagram

06763-032

The input to the DDS is a 48-bit FTW that provides the accu- mulator with a seed value. On each cycle of fS, the accumulator adds the value of the FTW to the running total of its output.

For example, given an FTW = 5, the accumulator increments the count by 5 sec on each fS cycle. Over time, the accumulator reaches the upper end of its capacity (248 in this case) and then rolls over, retaining the excess. The average rate at which the accumulator rolls over establishes the frequency of the output sinusoid. The following equation defines the average rollover rate of the accumulator and establishes the output frequency (fDDS) of the DDS:

FTW

fDDS = 

 

fS

248

Solving this equation for FTW yields

48

 

 



 

f DDS

FTW = round 2

 

 

 

 

 

 

 

f

S

 

 

 

For example, given that fS = 1 GHz and fDDS = 19.44 MHz, then FTW = 5,471,873,547,255 (0x04FA05143BF7).

The relative phase of the sinusoid can be controlled numerically, as well. This is accomplished using the phase offset function of the DDS (a programmable 14-bit value (Δphase); see the I/O Register Map section). The resulting phase offset, ΔΦ (radians), is given by

∆Φ = 2π ∆phase   14   2 

DIGITAL-TO-ANALOG (DAC) OUTPUT

The output of the digital core of the DDS is a time series of numbers representing a sinusoidal waveform. This series is translated to an analog signal by means of a digital-to-analog converter (DAC).

The DAC outputs its signal to two pins driven by a balanced current source architecture (see the DAC output diagram in Figure 41). The peak output current derives from a combination of two factors. The first is a reference current (IDAC_REF) that is established at the DAC_RSET pin, and the second is a scale factor that is programmed into the I/O register map.

The value of IDAC_REF is set by connecting a resistor (RDAC_REF) between the DAC_RSET pin and ground. The DAC_RSET pin

is internally connected to a virtual voltage reference of 1.2 V nominal, so the reference current can be calculated by

I DAC _ REF

=

1.2

RDAC _ REF

 

 

Note that the recommended value of IDAC_REF is 120 μA, which leads to a recommended value for RDAC_REF of 10 kΩ.

The scale factor consists of a 10-bit binary number (FSC) programmed into the DAC full-scale current register in the I/O register map. The full-scale DAC output current (IDAC_FS) is given by

 

 

192FSC

I DAC _ FS

= I DAC _ REF  72

+

 

 

 

 

1024 

Using the recommended value of RDAC_REF, the full-scale DAC output current can be set with 10-bit granularity over a range of approximately 8.6 mA to 31.7 mA. 20 mA is the default value.

 

 

 

 

 

 

 

 

 

 

 

 

AVDD3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

49

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IFS/2

 

 

IFS

 

IFS/2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CURRENT

 

 

 

 

 

 

SWITCH

 

 

 

CURRENT

 

 

 

SWITCH

 

 

 

 

 

 

 

 

 

SWITCH

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

ARRAY

 

 

 

 

 

 

 

 

ARRAY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IFS/2 + ICODE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IFS/2 – ICODE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DAC_OUT 50

 

 

 

 

 

 

 

 

 

 

 

CODE

 

 

 

 

 

 

 

51 DAC_OUTB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTERNAL

 

 

 

INTERNAL

 

 

 

 

 

 

 

 

 

 

 

 

 

50Ω

 

 

 

 

50Ω

 

 

 

 

-033

 

 

 

 

 

 

 

 

 

 

 

 

52

 

 

 

 

 

 

 

 

 

 

06763

 

 

 

 

 

 

 

 

 

 

 

 

 

AVSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 41. DAC Output

RECONSTRUCTION FILTER

The origin of the output clock signal produced by the AD9912 is the combined DDS and DAC. The DAC output signal appears as a sinusoid sampled at fS. The frequency of the sinusoid is determined by the frequency tuning word (FTW) that appears at the input to the DDS. The DAC output is typically passed through an external reconstruction filter that serves to remove the artifacts of the sampling process and other spurs outside the filter bandwidth. If desired, the signal can then be brought back on-chip to be converted to a square wave that is routed internally to the output clock driver or the 2× DLL multiplier.

Rev. D Page 17 of 40

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Contents Basic Block Diagram FeaturesApplications General DescriptionTable of Contents Parameter Min Typ Max Unit Test Conditions/Comments SpecificationsDC Specifications Clock Output Drivers Total Power DissipationSystem Clock Input Parameter Min Typ Max Unit Test Conditions/Comments AC SpecificationsAvss − Thermal Resistance Absolute Maximum RatingsESD Caution Parameter RatingInput Pin No Output Pin Type Mnemonic Description PIN Configuration and Function DescriptionsIoupdate ResetGND Avss OutbVideo BW Typical Performance CharacteristicsAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Direct Digital Synthesizer DDS Theory of OperationOverview Reconstruction Filter DIGITAL-TO-ANALOG DAC OutputSolving this equation for FTW yields 1024 DAC Spectrum vs. Reconstruction Filter Response Fdbkin InputsSysclk PLL Doubler Sysclk InputsFunctional Description Sysclk PLL multiplier has a 1 GHz VCO at its core Sysclk PLL MultiplierDetail of Sysclk Differential Inputs External Loop Filter Sysclk PLLHarmonic Spur Reduction Output Clock Drivers and 2× Frequency MultiplierSpur Reduction Circuit Diagram Thermal Parameters Thermal PerformanceDefault Output Frequency on POWER-UP POWER-UPPOWER-ON Reset Supplies Power Supply PartitioningOperation of Serial Control Port Serial Control PortSerial Control Port PIN Descriptions Instruction Word 16 Bits MSB/LSB First TransfersRead Operations are changed to LSB first orderI15 I14 I13 I12 I11 I10 A12 A11 A10 Serial Control Port, 16-Bit Instruction Word, MSB FirstParameter Description PLL Register MAPHSR-A Register 0x0010-Power-Down and Enable Register 0x0000-Serial Port ConfigurationPower-up default is defined by the start-up pins Register DescriptionsRegister 0x0013-Reset Not Autoclearing Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0020-N-Divider Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x0105-S-Divider Register 0x0106-S-DividerRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x0201-CMOS Driver Register 0x0200-HSTL DriverRegister 0x040C-DAC Full-Scale Current Register 0x040D to Register 0x0410-ReservedRegister 0x0504-Spur a Register 0x0503-Spur aRegister 0x0505-Spur B Register 0x0506-Spur BOutline Dimensions Ordering Guide Model Temperature Range Package Description Package OptionAD9912BCPZ1 AD9912BCPZ-REEL71Rev. D Page 40
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