Analog Devices AD9912 Fdbkin Inputs, DAC Spectrum vs. Reconstruction Filter Response

Page 18

AD9912

MAGNITUDE

(dB)

 

IMAGE 0

IMAGE 1

IMAGE 2

IMAGE 3

 

IMAGE 4

0

 

 

 

 

 

 

–20

 

 

 

 

 

 

–40

PRIMARY

FILTER

 

 

 

 

SIGNAL

RESPONSE

 

SIN(x)/x

 

 

 

 

 

 

–60

 

 

 

ENVELOPE

 

 

 

 

 

 

 

 

–80

SPURS

 

 

 

 

 

–100

 

 

 

 

 

 

 

BASE BAND

fs/2

fs

3fs/2

2fs

5fs/2

 

 

 

 

 

 

Figure 42. DAC Spectrum vs. Reconstruction Filter Response

f

06763-034

Because the DAC constitutes a sampled system, its output must be filtered so that the analog waveform accurately represents the digital samples supplied to the DAC input. The unfiltered DAC output contains the (typically) desired baseband signal, which extends from dc to the Nyquist frequency (fS/2). It also contains images of the baseband signal that theoretically extend to infinity. Notice that the odd images (shown in Figure 42) are mirror images of the baseband signal. Furthermore, the entire DAC output spectrum is affected by a sin(x)/x response, which is caused by the sample-and-hold nature of the DAC output signal.

For applications using the fundamental frequency of the DAC output, the response of the reconstruction filter should preserve the baseband signal (Image 0), while completely rejecting all other images. However, a practical filter implementation typically exhibits a relatively flat pass band that covers the desired output frequency plus 20%, rolls off as steeply as possible, and then maintains significant (though not complete) rejection of the remaining images. Depending on how close unwanted spurs are to the desired signal, a third-, fifth-, or seventh-order elliptic low-pass filter is common.

Some applications operate off an image above the Nyquist frequency, and those applications use a band-pass filter instead of a low-pass filter.

The design of the reconstruction filter has a significant impact on the overall signal performance. Therefore, good filter design and implementation techniques are important for obtaining the best possible jitter results.

FDBK_IN INPUTS

The FDBK_IN pins serve as the input to the comparators and output drivers of the AD9912. Typically, these pins are used to receive the signal generated by the DDS after it has been band- limited by the external reconstruction filter.

A diagram of the FDBK_IN input pins is provided in Figure 43, which includes some of the internal components used to bias the input circuitry. Note that the FDBK_IN input pins are internally biased to a dc level of ~1 V. Care should be taken to ensure that any external connections do not disturb the dc bias because this may significantly degrade performance.

FDBK_IN

 

TO S-DIVIDER

 

 

 

 

~1pF

15kΩ

AND CLOCK

 

OUTPUT SECTION

AVSS

 

 

 

 

~1pF

15kΩ

 

 

FDBK_INB

 

 

 

+

 

 

 

~1V

 

~2pF

-035

 

 

 

AVSS 06763

Figure 43. Differential FDBK_IN Inputs

Rev. D Page 18 of 40

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Contents Applications FeaturesBasic Block Diagram General DescriptionTable of Contents Specifications DC SpecificationsParameter Min Typ Max Unit Test Conditions/Comments Total Power Dissipation System Clock InputClock Output Drivers AC Specifications Parameter Min Typ Max Unit Test Conditions/CommentsAvss − ESD Caution Absolute Maximum RatingsThermal Resistance Parameter RatingPIN Configuration and Function Descriptions Input Pin No Output Pin Type Mnemonic DescriptionGND Avss ResetIoupdate OutbTypical Performance Characteristics Video BWAbsolute Phase Noise Using Hstl Driver DDS Run at 200 Msps for 10 MHz Plot Absolute Phase Noise of Unfiltered DAC Output, fOUT = 63 MHz Cmos Output Driver Waveform @ 3.3 INPUT/OUTPUT Termination Recommendations Theory of Operation OverviewDirect Digital Synthesizer DDS Solving this equation for FTW yields DIGITAL-TO-ANALOG DAC OutputReconstruction Filter 1024 Fdbkin Inputs DAC Spectrum vs. Reconstruction Filter ResponseSysclk Inputs Functional DescriptionSysclk PLL Doubler Detail of Sysclk Differential Inputs Sysclk PLL MultiplierSysclk PLL multiplier has a 1 GHz VCO at its core External Loop Filter Sysclk PLLOutput Clock Drivers and 2× Frequency Multiplier Harmonic Spur ReductionSpur Reduction Circuit Diagram Thermal Performance Thermal ParametersPOWER-UP POWER-ON ResetDefault Output Frequency on POWER-UP Power Supply Partitioning SuppliesSerial Control Port Serial Control Port PIN DescriptionsOperation of Serial Control Port Read MSB/LSB First TransfersInstruction Word 16 Bits Operations are changed to LSB first orderSerial Control Port, 16-Bit Instruction Word, MSB First I15 I14 I13 I12 I11 I10 A12 A11 A10Parameter Description Register MAP PLLHSR-A Power-up default is defined by the start-up pins Register 0x0000-Serial Port ConfigurationRegister 0x0010-Power-Down and Enable Register DescriptionsRegister 0x0020-N-Divider Register 0x0011-Reserved Register 0x0012-Reset AutoclearingRegister 0x0013-Reset Not Autoclearing Register 0x0021-Reserved Register 0x0022-PLL ParametersRegister 0x0105-S-Divider Register 0x01A7-FTW0 Frequency Tuning WordRegister 0x01A8-FTW0 Frequency Tuning Word Register 0x0106-S-DividerRegister 0x01AB-FTW0 Frequency Tuning Word Register 0x01A9-FTW0 Frequency Tuning WordRegister 0x01AA-FTW0 Frequency Tuning Word Register 0x01AC-PhaseRegister 0x040C-DAC Full-Scale Current Register 0x0200-HSTL DriverRegister 0x0201-CMOS Driver Register 0x040D to Register 0x0410-ReservedRegister 0x0505-Spur B Register 0x0503-Spur aRegister 0x0504-Spur a Register 0x0506-Spur BOutline Dimensions AD9912BCPZ1 Model Temperature Range Package Description Package OptionOrdering Guide AD9912BCPZ-REEL71Rev. D Page 40
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