Intel 273246-002 Flash Bios VPP Select J21, Flash Bios Boot Block Control J22, Cmos RAM Clear J24

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Hardware Reference

4.7.4Flash BIOS VPP Select (J21)

This jumper controls the voltage presented to the flash BIOS VPP pin. The 2-3 position supplies

5 V and is the default for normal operation. This position inhibits programming or erasing the flash BIOS.

The 1-2 position supplies 12 V and should only be used if directed to do so by a utility that is used to reprogram the BIOS.

4.7.5Flash BIOS Boot Block Control (J22)

This jumper controls the Boot Block protection of the flash BIOS. When this jumper is in the 2-3 position, the boot block is locked and cannot be programmed. This is the default position of this jumper.

The 1-2 position unlocks the boot block so that it can be erased and reprogrammed. This position should only be used under the direction of a utility that is designed to reprogram the boot block of the flash device.

4.7.6SMI# Source Control (J23)

This jumper selects the source of the SMI# interrupt to the processor. Only the 2-3 position which selects the PIIX4E is supported. The 1-2 position is reserved for future use.

4.7.7CMOS RAM Clear (J24)

This jumper controls power to the battery backed-up CMOS RAM. This RAM is used to store information about the system configuration that is required by the BIOS. The 1-2 position is for normal operation. The 2-3 position allows for the RAM to be cleared.

To clear the RAM perform the following steps:

1.Remove power from the evaluation platform by removing jumper J20

2.Move J24 to the 2-3.

3.Disconnect the power supply (J11).

4.Install J24 in the 1-2 position.

5.Reconnect the power supply (J11).

6.Reboot the system and enter the BIOS setup screen to configure the system.

4.7.8Push Button Switches

There are two push button switches on the evaluation board labeled S1 and S2.

S1 is non-functional and reserved for future use.

S2 is the reset button. Press S2 to force a hardware reset of the system.

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Celeron™ Processor Development Kit Manual

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Contents Celeron Processor Development Kit ManualCeleron Processor Development Kit Manual Contents Hardware Reference Figures TablesPage Content Overview Text ConventionsTechnical Support Electronic Support SystemsProduct Literature Telephone Technical SupportRelated Documents Processor Assembly Features OverviewBaseboard Features Included HardwareSoftware Key Features General Software, IncBefore You Begin VGA MonitorSetting up the Evaluation Board Evaluation Board Jumpers and ConnectorsGetting Started Configuring the Bios Page Block Diagram Evaluation Board Block Diagram2 82443BX Host Bridge/Controller System OperationCeleron Processor 3 ITP System Bus Interface4 82371EB PCI to ISA/IDE Xcelerator PIIX4E PowerBoot ROM DramAGP Connector PCI ConnectorsISA Connectors IDE SupportInterrupt Map Post Code DebuggerClock Generation InterruptsSize Description Memory MapMemory Map Page Thermal Management Processor AssemblyPost Code Debugger ITP Debugger PortPCI Device Mapping ISA and PCI Expansion SlotsPCI Device Mapping Device Address Line PCI Device NumberPrimary Power Connector J11 Connector PinoutsATX Power Connector Pin Name FunctionUSB Connector Pinout J2 ITP Debugger ConnectorITP Connector Pin Assignment J2 on the Processor Assembly Stacked USBDB25 Parallel Port Connector Pinout J3 Mouse and Keyboard ConnectorsKeyboard and Mouse Connector Pinouts J1 on the Baseboard Pin Signal NamePCI IDE1 JP3 and IDE2 JP4 Connector IDE ConnectorSerial Port Connector Pinout J4 Serial PortsFloppy Drive Connector Diskette Drive Header Connector JP1PCI Slot Connector 10. PCI Slots J7, J8, J9ISA Slot Connector 11. ISA Slots J5, J6Pin# AGP Connector12. AGP Slot J13 Jumpers Enable Spread Spectrum Clocking J1413. Default Jumper Settings Clock Frequency Selection J15Push Button Switches Flash Bios VPP Select J21Flash Bios Boot Block Control J22 6 SMI# Source Control J23In-Circuit Bios Update Page Bios and Pre-Boot Features Power-On Self-Test PostBios Post Pre-Boot Environment Setup Screen System Basic Cmos Configuration ScreenConfiguring Drive Assignments Embedded Bios Basic Setup ScreenFile System Name Controller Master/Slave Configuring IDE Drive TypesIDE0-IDE3 Drive Assignments Configuring Boot Actions Custom Configuration Setup ScreenShadow Configuration Setup Screen Embedded Bios Custom Setup ScreenStandard Diagnostics Routines Setup Screen Start System Bios Debugger Setup ScreenConsole Redirection Start RS232 Manufacturing Link Setup ScreenManufacturing Mode Integrated Bios Debugger CE-Ready Windows CE LoaderIntegrated Bios Debugger Running Over a Remote Terminal Embedded Bios Post Codes Poststatusvideorom Poststatusbeforesetup Embedded Bios Beep Codes PostbeeprefreshPage PLD Code Listing PLD Code Listing Table B-1. Baseboard Bill of Materials Sheet 1 Reference Description Manufacturer Manufacturer P/NBios Flash Intel Table B-1. Baseboard Bill of Materials Sheet 2Table B-1. Baseboard Bill of Materials Sheet 3 Reference Description ManufacturerTable B-1. Baseboard Bill of Materials Sheet 4 SOIC20,SO20WReference Descriptions Manufacturer Manufacturer P/N ECJ-1VB1C104KERJ-6GEYJ472V Schematics Evaluation Platform System Electronic s Board PCI BUS Mini PCI Connector This Drawing Contains Information Which has not Socket DIMM1 DIMM2 This Drawing Contains Information Which has not This Drawing Contains Information Which Hasnot PCI Slot PCI Slot Been Verified for Manufacturing AS AN END Seru Title Been Verified for Manufacturing AS AN Enduser Title USB Secondary IDE Connector ISA/Host USB Connectors ISA Slots COM0/COM1 Port Speaker Header Unused Gates CeleronTM Processor Ppga Daughter Board ITP Pin Socket PRODUCT. Intel is not Responsible for GTL+ Termination RESISTORS-BX GTL+ Termination RESISTORS-CPU 82443BX BX Strapping Options Mounting Holes Thermal Sensor TIE Directly to Ground Plane Index Index-2