Intel 273246-002 manual Been Verified for Manufacturing AS AN END Seru Title

Page 77

 

A

B

C

D

E

 

4

 

 

 

V 3 _ 3

 

 

 

 

 

 

C 1 8 6

C 1 8 5

C 1 8 4

C 1 7 9

C 1 7 8

C 1 6 6

C 1 6 7

C 1 7 7

C 1 7 2

C 1 8 0

0 . 01uF

0 . 01uF

0 . 01uF

0 . 01uF

0 . 01uF

0 . 01uF

0 . 01uF

0 . 01uF

0 . 01uF

0 . 01uF

Pin A3 is tied to ground per AGP Specification

Rev 1.0

4

4 SBA[7:0]

V 3 _ 3

V 3 _ 3

V 3 _ 3

V 5 _ 0

+ 1 2 V V 3 _ 3

3

2

1

3,9,10,11,13,14 PIRQC#

Stub length from connector to resistor must be less than 0.1"

 

 

 

V 3 _ 3

G A D _ S T B 0

R87

8 .2K

 

G A D _ S T B 1

R77

8 .2K

 

G S B _ S T B

R76

8 .2K

 

G F R A M E #

R78

8 .2K

 

GIRDY#

R79

8 .2K

 

GTRDY#

R80

8 .2K

 

G S T O P #

R82

8 .2K

 

GDEVSEL#

R81

8 .2K

 

G R E Q #

R72

8 .2K

 

G G N T #

R73

8 .2K

V3.3SUS

GPIPE#

R74

8 .2K

 

G R B F #

R75

8 .2K

 

GPAR

R86

8 .2K

 

G P M E #

R84

8 .2K

 

 

 

V 5 _ 0

 

 

R64

 

 

4 .7K

 

U2A

1 4

 

 

2

 

1

 

 

7

 

7 4 A S 0 7

 

V 3 _ 3

4 G C L K

4 G R E Q #

4 G S T 0

4 G S T 2

4 G R B F #

4 G S B _ S T B

4 G A D _ S T B 1

4 GIRDY#

4 GDEVSEL#

R83

8 .2K

R85

8 .2K

4 G A D _ S T B 0

4 GAD[31:0]

4 GC/BE#[3:0]

SBA0

SBA2

SBA4

SBA6

G A D 3 1

G A D 2 9

G A D 2 7

G A D 2 5

G A D 2 3

G A D 2 1

G A D 1 9

G A D 1 7

GC/BE#2

GC/BE#1

G A D 1 4

G A D 1 2

G A D 1 0

G A D 8

G A D 7

G A D 5

G A D 3

G A D 1

 

J13

 

 

B 1

OVRCNT#

1 2 V

A 1

B 2

A 2

5 . 0V

SPARE

B 3

A 3

5 . 0V

RESERVED

B 4

A 4

USB+

USB-

B 5

A 5

GND

GND

B 6

A 6

INTB#

INTA#

B 7

A 7

CLK

R S T #

B 8

A 8

R E Q #

G N T #

B 9

A 9

3 . 3V

3 .3V

B 1 0

A 1 0

S T 0

S T 1

B 1 1

A 1 1

S T 2

RESERVED

B 1 2

A 1 2

RBF#

PIPE#

B 1 3

A 1 3

GND

GND

B 1 4

A 1 4

SPARE

SPARE

B 1 5

A 1 5

SBA0

SBA1

B 1 6

A 1 6

3 . 3V

3 .3V

B 1 7

A 1 7

SBA2

SBA3

B 1 8

A 1 8

S B _ S T B

RESERVED

B 1 9

A 1 9

GND

GND

B 2 0

A 2 0

SBA4

SBA5

B 2 1

A 2 1

SBA6

SBA7

 

 

B 2 6

AD31

AD30

A 2 6

B 2 7

A 2 7

AD29

AD28

B 2 8

A 2 8

3 . 3V

3 .3V

B 2 9

A 2 9

AD27

AD26

B 3 0

A 3 0

AD25

AD24

B 3 1

A 3 1

GND

GND

B 3 2

A 3 2

A D _ S T B 1

RESERVED

B 3 3

A 3 3

AD23

C/BE3#

B 3 4

A 3 4

VDDQ3 . 3

VDDQ3 . 3

B 3 5

A 3 5

AD21

AD22

B 3 6

A 3 6

AD19

AD20

B 3 7

A 3 7

GND

GND

B 3 8

A 3 8

AD17

AD18

B 3 9

A 3 9

C/BE2#

AD16

B 4 0

A 4 0

VDDQ3 . 3

VDDQ3 . 3

B 4 1

A 4 1

IRDY#

FRAME#

B 4 2

A 4 2

SPARE

NC

B 4 3

A 4 3

GND

GND

B 4 4

A 4 4

SPARE

NC

B 4 5

A 4 5

3 . 3V

3 .3V

B 4 6

A 4 6

DEVSEL#

TRDY#

B 4 7

A 4 7

VDDQ3 . 3

S T O P #

B 4 8

A 4 8

PERR#

P M E #

B 4 9

A 4 9

GND

GND

B 5 0

A 5 0

SERR#

PAR

B 5 1

A 5 1

C/BE1#

AD15

B 5 2

A 5 2

VDDQ3 . 3

VDDQ3 . 3

B 5 3

A 5 3

AD14

AD13

B 5 4

A 5 4

AD12

AD11

B 5 5

A 5 5

GND

GND

B 5 6

A 5 6

AD10

AD9

B 5 7

A 5 7

AD8

C/BE0#

B 5 8

A 5 8

VDDQ3 . 3

3 .3V

B 5 9

A 5 9

A D _ S T B 0

RESERVED

B 6 0

A 6 0

AD7

AD6

B 6 1

A 6 1

GND

GND

B 6 2

A 6 2

AD5

AD4

B 6 3

A 6 3

AD3

AD2

B 6 4

A 6 4

VDDQ3 . 3

VDDQ3 . 3

B 6 5

A 6 5

AD1

AD0

B 6 6

A 6 6

S M B 0

S M B 1

 

 

AGP Connector

SBA1

SBA3

SBA5

SBA7

G A D 3 0 G A D 2 8

G A D 2 6 G A D 2 4

GC/BE#3

G A D 2 2 G A D 2 0

G A D 1 8 G A D 1 6

G A D 1 5

G A D 1 3 G A D 1 1

G A D 9 GC/BE#0

G A D 6

G A D 4

G A D 2

G A D 0

 

 

R65

V 5 _ 0

 

 

 

 

4 .7K

 

 

 

 

 

1 4

U2B

 

 

 

 

3

4

PIRQB#

3,9,10,11,13,14

-PCIRST

3,4,10,11,13

 

 

7

 

 

 

G G N T #

4

7 4 A S 0 7

 

 

 

 

 

 

 

 

 

 

G S T 1

4

 

 

 

 

GPIPE#

4

 

 

 

 

G F R A M E #

4

GTRDY#

4

G S T O P #

4

G P M E #

1 4

GPAR

4

3

2

1

THIS DRAWING CONTAINS INFORMATION WHICH HASNOT

 

 

BEEN VERIFIED FOR MANUFACTURING AS AN END SERU Title

 

PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE

 

AGP Connector

MISUSE OF THIS INFORMATIO.

Size Document Number

Rev

C

D

 

 

 

 

 

Date:

Thursday, February 25, 1999

Sheet

1 2

of

2 2

 

 

A

B

C

D

 

E

 

 

 

 

 

Page 76 Page 78
Image 77
Page 76 Page 78
Contents Development Kit Manual Celeron ProcessorCeleron Processor Development Kit Manual Contents Hardware Reference Tables FiguresPage Text Conventions Content OverviewElectronic Support Systems Technical SupportTelephone Technical Support Product LiteratureRelated Documents Overview Processor Assembly FeaturesIncluded Hardware Baseboard FeaturesGeneral Software, Inc Software Key FeaturesVGA Monitor Before You BeginEvaluation Board Jumpers and Connectors Setting up the Evaluation BoardGetting Started Configuring the Bios Page Evaluation Board Block Diagram Block Diagram2 82443BX Host Bridge/Controller System OperationCeleron Processor System Bus Interface 3 ITPBoot ROM Power4 82371EB PCI to ISA/IDE Xcelerator PIIX4E DramISA Connectors PCI ConnectorsAGP Connector IDE SupportClock Generation Post Code DebuggerInterrupt Map InterruptsSize Description Memory MapMemory Map Page Post Code Debugger Processor AssemblyThermal Management ITP Debugger PortPCI Device Mapping ISA and PCI Expansion SlotsPCI Device Mapping Device Address Line PCI Device NumberATX Power Connector Connector PinoutsPrimary Power Connector J11 Pin Name FunctionITP Connector Pin Assignment J2 on the Processor Assembly ITP Debugger ConnectorUSB Connector Pinout J2 Stacked USBKeyboard and Mouse Connector Pinouts J1 on the Baseboard Mouse and Keyboard ConnectorsDB25 Parallel Port Connector Pinout J3 Pin Signal NameSerial Port Connector Pinout J4 IDE ConnectorPCI IDE1 JP3 and IDE2 JP4 Connector Serial PortsDiskette Drive Header Connector JP1 Floppy Drive Connector10. PCI Slots J7, J8, J9 PCI Slot Connector11. ISA Slots J5, J6 ISA Slot ConnectorPin# AGP Connector12. AGP Slot J13 13. Default Jumper Settings Enable Spread Spectrum Clocking J14Jumpers Clock Frequency Selection J15Flash Bios Boot Block Control J22 Flash Bios VPP Select J21Push Button Switches 6 SMI# Source Control J23In-Circuit Bios Update Page Power-On Self-Test Post Bios and Pre-Boot FeaturesBios Post Pre-Boot Environment Basic Cmos Configuration Screen Setup Screen SystemEmbedded Bios Basic Setup Screen Configuring Drive AssignmentsFile System Name Controller Master/Slave Configuring IDE Drive TypesIDE0-IDE3 Drive Assignments Custom Configuration Setup Screen Configuring Boot ActionsEmbedded Bios Custom Setup Screen Shadow Configuration Setup ScreenStart System Bios Debugger Setup Screen Standard Diagnostics Routines Setup ScreenConsole Redirection Start RS232 Manufacturing Link Setup ScreenManufacturing Mode CE-Ready Windows CE Loader Integrated Bios DebuggerIntegrated Bios Debugger Running Over a Remote Terminal Embedded Bios Post Codes Poststatusvideorom Poststatusbeforesetup Postbeeprefresh Embedded Bios Beep CodesPage PLD Code Listing PLD Code Listing Reference Description Manufacturer Manufacturer P/N Table B-1. Baseboard Bill of Materials Sheet 1Table B-1. Baseboard Bill of Materials Sheet 2 Bios Flash IntelReference Description Manufacturer Table B-1. Baseboard Bill of Materials Sheet 3SOIC20,SO20W Table B-1. Baseboard Bill of Materials Sheet 4ECJ-1VB1C104K Reference Descriptions Manufacturer Manufacturer P/NERJ-6GEYJ472V Schematics Evaluation Platform System Electronic s Board PCI BUS Mini PCI Connector This Drawing Contains Information Which has not Socket DIMM1 DIMM2 This Drawing Contains Information Which has not This Drawing Contains Information Which Hasnot PCI Slot PCI Slot Been Verified for Manufacturing AS AN END Seru Title Been Verified for Manufacturing AS AN Enduser Title USB Secondary IDE Connector ISA/Host USB Connectors ISA Slots COM0/COM1 Port Speaker Header Unused Gates CeleronTM Processor Ppga Daughter Board ITP Pin Socket PRODUCT. Intel is not Responsible for GTL+ Termination RESISTORS-BX GTL+ Termination RESISTORS-CPU 82443BX BX Strapping Options Mounting Holes Thermal Sensor TIE Directly to Ground Plane Index Index-2
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