Intel 273246-002 manual CE-Ready Windows CE Loader, Integrated Bios Debugger

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BIOS Quick Reference

The software on the target can be any terminal emulation program that supports ANSI terminal mode, using 9600 baud, no parity, and one stop bit (Note: This can be modified by the OEM during BIOS adaptation.) The program must be set to not use flow control, or the console may seem to stall or not accept input.

Caution: HYPERTERMINAL’s default setting is to use flow control, which will render the console inoperative. To change this, create a new session, change the flow control setting to “none”, save the session, and exit HYPERTERMINAL. Then reinvoke HYPERTERMINAL with the session and it will operate with the new flow control setting.

5.10.2CE-Ready Windows CE Loader

Your system’s BIOS is “CE-Ready” and can directly boot Windows CE* without loading an intermediate operating system such as DOS and LOADCEPC. Instead, the NK.BIN file can be placed on a disk drive or drive emulator, and then the BIOS can be configured through the Basic CMOS Configuration Setup Screen to boot the NK.BIN file from the boot drives instead of the boot records on those drives.

To configure your system to boot Windows CE natively from a disk drive, set the “Boot Method” field to “Windows CE” in the Basic CMOS Configuration Setup Screen. Then, place a copy of NK.BIN suitable for execution by LOADCEPC in the root directory of your normal boot drive, such as drive C:. Then, reboot the system. The configuration box should be displayed (Figure 5-8), and immediately following should be the message “Loading Windows CE…” followed by a series of dots, indicating that the loading process is continuing. Once fully loaded, Windows CE takes over the system and runs using the standard PC keyboard, screen, and PS/2 mouse.

Figure 5-8. CE-Ready Boot Feature

5.10.3Integrated BIOS Debugger

The system’s BIOS contains a built-in debugger that can be a valuable tool to aid the board bring- up process on new designs similar to the evaluation board. It supports a DOS SYMDEB-style command line interface, and can be used on the main console’s keyboard and screen, or over a redirected connection to a terminal program (see “Console Redirection” on page 5-9).

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Celeron™ Processor Development Kit Manual

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Contents Celeron Processor Development Kit ManualCeleron Processor Development Kit Manual Contents Hardware Reference Figures TablesPage Content Overview Text ConventionsTechnical Support Electronic Support SystemsProduct Literature Telephone Technical SupportRelated Documents Processor Assembly Features OverviewBaseboard Features Included HardwareSoftware Key Features General Software, IncBefore You Begin VGA MonitorSetting up the Evaluation Board Evaluation Board Jumpers and ConnectorsGetting Started Configuring the Bios Page Block Diagram Evaluation Board Block Diagram2 82443BX Host Bridge/Controller System OperationCeleron Processor 3 ITP System Bus Interface4 82371EB PCI to ISA/IDE Xcelerator PIIX4E PowerBoot ROM DramAGP Connector PCI ConnectorsISA Connectors IDE SupportInterrupt Map Post Code DebuggerClock Generation InterruptsSize Description Memory MapMemory Map Page Thermal Management Processor AssemblyPost Code Debugger ITP Debugger PortPCI Device Mapping ISA and PCI Expansion SlotsPCI Device Mapping Device Address Line PCI Device NumberPrimary Power Connector J11 Connector PinoutsATX Power Connector Pin Name FunctionUSB Connector Pinout J2 ITP Debugger ConnectorITP Connector Pin Assignment J2 on the Processor Assembly Stacked USBDB25 Parallel Port Connector Pinout J3 Mouse and Keyboard ConnectorsKeyboard and Mouse Connector Pinouts J1 on the Baseboard Pin Signal NamePCI IDE1 JP3 and IDE2 JP4 Connector IDE ConnectorSerial Port Connector Pinout J4 Serial PortsFloppy Drive Connector Diskette Drive Header Connector JP1PCI Slot Connector 10. PCI Slots J7, J8, J9ISA Slot Connector 11. ISA Slots J5, J6Pin# AGP Connector12. AGP Slot J13 Jumpers Enable Spread Spectrum Clocking J1413. Default Jumper Settings Clock Frequency Selection J15Push Button Switches Flash Bios VPP Select J21Flash Bios Boot Block Control J22 6 SMI# Source Control J23In-Circuit Bios Update Page Bios and Pre-Boot Features Power-On Self-Test PostBios Post Pre-Boot Environment Setup Screen System Basic Cmos Configuration ScreenConfiguring Drive Assignments Embedded Bios Basic Setup ScreenFile System Name Controller Master/Slave Configuring IDE Drive TypesIDE0-IDE3 Drive Assignments Configuring Boot Actions Custom Configuration Setup ScreenShadow Configuration Setup Screen Embedded Bios Custom Setup ScreenStandard Diagnostics Routines Setup Screen Start System Bios Debugger Setup ScreenConsole Redirection Start RS232 Manufacturing Link Setup ScreenManufacturing Mode Integrated Bios Debugger CE-Ready Windows CE LoaderIntegrated Bios Debugger Running Over a Remote Terminal Embedded Bios Post Codes Poststatusvideorom Poststatusbeforesetup Embedded Bios Beep Codes PostbeeprefreshPage PLD Code Listing PLD Code Listing Table B-1. Baseboard Bill of Materials Sheet 1 Reference Description Manufacturer Manufacturer P/NBios Flash Intel Table B-1. Baseboard Bill of Materials Sheet 2Table B-1. Baseboard Bill of Materials Sheet 3 Reference Description ManufacturerTable B-1. Baseboard Bill of Materials Sheet 4 SOIC20,SO20WReference Descriptions Manufacturer Manufacturer P/N ECJ-1VB1C104KERJ-6GEYJ472V Schematics Evaluation Platform System Electronic s Board PCI BUS Mini PCI Connector This Drawing Contains Information Which has not Socket DIMM1 DIMM2 This Drawing Contains Information Which has not This Drawing Contains Information Which Hasnot PCI Slot PCI Slot Been Verified for Manufacturing AS AN END Seru Title Been Verified for Manufacturing AS AN Enduser Title USB Secondary IDE Connector ISA/Host USB Connectors ISA Slots COM0/COM1 Port Speaker Header Unused Gates CeleronTM Processor Ppga Daughter Board ITP Pin Socket PRODUCT. Intel is not Responsible for GTL+ Termination RESISTORS-BX GTL+ Termination RESISTORS-CPU 82443BX BX Strapping Options Mounting Holes Thermal Sensor TIE Directly to Ground Plane Index Index-2