Intel 273246-002 manual Unused Gates

Page 87

 

A

B

C

D

E

 

4

3

V 5 _ 0

1 4

9

7

1 4

1 1

7

1 4

1 3

7

Make these connections Cutable

V3.3SUS

1 4 U24F

1 3

1 2

7

7 4 L C T 14

U21D

8

74HCT14

U21E

1 0

74HCT14

U21F

1 2

74HCT14

V 5 _ 0

1 4 U2C

5 6

7

7 4 A S 0 7

1 4 U2D

9 8

7

7 4 A S 0 7

1 4 U2E

1 1 1 0

7

7 4 A S 0 7

1 4 U2F

1 3 1 2

7

7 4 A S 0 7

Make these connections

Cutable

V 5 _ 0

V3.3SUS

 

 

 

 

 

 

 

 

 

 

 

 

1 4

4

 

 

 

 

 

 

5

 

6

 

 

7

 

 

 

 

 

 

 

 

 

U15B

 

 

 

 

 

 

7 4 L V C 1 2 5

 

 

 

 

 

 

 

 

 

 

 

 

1 4

10

 

 

 

 

 

 

9

 

8

 

 

7

 

 

 

 

 

 

 

 

 

U15C

 

 

 

 

 

 

7 4 L V C 1 2 5

 

 

 

 

 

 

 

 

 

 

 

 

1 4

13

 

 

 

 

 

 

1 2

 

1 1

7

 

 

 

Make these connections

U15D

Cutable

7 4 L V C 1 2 5

V 5 _ 0

4

3

1 4

U25D

2

1

Make these connections Cutable

1 4 U22C

9

8

1 0

7

7 4 A L S 0 0

1 4 U22D

1 2

1 1

1 3

7

7 4 A L S 0 0

Make these connections

Cutable

9

7

1 4

1 1

7

1 4

1 3

7

Make these connections Cutable

8

7 4 A C T 0 5

U25E

1 0

7 4 A C T 0 5

U25F

1 2

7 4 A C T 0 5

2

1

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT

 

 

 

 

BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER

Title

Unused Gates

 

 

PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE

 

 

 

 

Size

Document Number

 

Rev

MISUSE OF THIS INFORMATIO.

C

{Doc}

 

D

 

 

 

 

Date:

Thursday, February 25, 1999

Sheet 2 2 of 2 2

 

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Image 87
Contents Development Kit Manual Celeron ProcessorCeleron Processor Development Kit Manual Contents Hardware Reference Tables FiguresPage Text Conventions Content OverviewElectronic Support Systems Technical SupportTelephone Technical Support Product LiteratureRelated Documents Overview Processor Assembly FeaturesIncluded Hardware Baseboard FeaturesGeneral Software, Inc Software Key FeaturesVGA Monitor Before You BeginEvaluation Board Jumpers and Connectors Setting up the Evaluation BoardGetting Started Configuring the Bios Page Evaluation Board Block Diagram Block DiagramSystem Operation Celeron Processor2 82443BX Host Bridge/Controller System Bus Interface 3 ITPDram PowerBoot ROM 4 82371EB PCI to ISA/IDE Xcelerator PIIX4EIDE Support PCI ConnectorsISA Connectors AGP ConnectorInterrupts Post Code DebuggerClock Generation Interrupt MapMemory Map Memory MapSize Description Page ITP Debugger Port Processor AssemblyPost Code Debugger Thermal ManagementDevice Address Line PCI Device Number ISA and PCI Expansion SlotsPCI Device Mapping PCI Device MappingPin Name Function Connector PinoutsATX Power Connector Primary Power Connector J11Stacked USB ITP Debugger ConnectorITP Connector Pin Assignment J2 on the Processor Assembly USB Connector Pinout J2Pin Signal Name Mouse and Keyboard ConnectorsKeyboard and Mouse Connector Pinouts J1 on the Baseboard DB25 Parallel Port Connector Pinout J3Serial Ports IDE ConnectorSerial Port Connector Pinout J4 PCI IDE1 JP3 and IDE2 JP4 ConnectorDiskette Drive Header Connector JP1 Floppy Drive Connector10. PCI Slots J7, J8, J9 PCI Slot Connector11. ISA Slots J5, J6 ISA Slot ConnectorAGP Connector 12. AGP Slot J13Pin# Clock Frequency Selection J15 Enable Spread Spectrum Clocking J1413. Default Jumper Settings Jumpers6 SMI# Source Control J23 Flash Bios VPP Select J21Flash Bios Boot Block Control J22 Push Button SwitchesIn-Circuit Bios Update Page Power-On Self-Test Post Bios and Pre-Boot FeaturesBios Post Pre-Boot Environment Basic Cmos Configuration Screen Setup Screen SystemEmbedded Bios Basic Setup Screen Configuring Drive AssignmentsConfiguring IDE Drive Types IDE0-IDE3 Drive AssignmentsFile System Name Controller Master/Slave Custom Configuration Setup Screen Configuring Boot ActionsEmbedded Bios Custom Setup Screen Shadow Configuration Setup ScreenStart System Bios Debugger Setup Screen Standard Diagnostics Routines Setup ScreenStart RS232 Manufacturing Link Setup Screen Manufacturing ModeConsole Redirection CE-Ready Windows CE Loader Integrated Bios DebuggerIntegrated Bios Debugger Running Over a Remote Terminal Embedded Bios Post Codes Poststatusvideorom Poststatusbeforesetup Postbeeprefresh Embedded Bios Beep CodesPage PLD Code Listing PLD Code Listing Reference Description Manufacturer Manufacturer P/N Table B-1. Baseboard Bill of Materials Sheet 1Table B-1. Baseboard Bill of Materials Sheet 2 Bios Flash IntelReference Description Manufacturer Table B-1. Baseboard Bill of Materials Sheet 3SOIC20,SO20W Table B-1. Baseboard Bill of Materials Sheet 4ECJ-1VB1C104K Reference Descriptions Manufacturer Manufacturer P/NERJ-6GEYJ472V Schematics Evaluation Platform System Electronic s Board PCI BUS Mini PCI Connector This Drawing Contains Information Which has not Socket DIMM1 DIMM2 This Drawing Contains Information Which has not This Drawing Contains Information Which Hasnot PCI Slot PCI Slot Been Verified for Manufacturing AS AN END Seru Title Been Verified for Manufacturing AS AN Enduser Title USB Secondary IDE Connector ISA/Host USB Connectors ISA Slots COM0/COM1 Port Speaker Header Unused Gates CeleronTM Processor Ppga Daughter Board ITP Pin Socket PRODUCT. Intel is not Responsible for GTL+ Termination RESISTORS-BX GTL+ Termination RESISTORS-CPU 82443BX BX Strapping Options Mounting Holes Thermal Sensor TIE Directly to Ground Plane Index Index-2