Intel 273246-002 manual Configuring Boot Actions, Custom Configuration Setup Screen

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BIOS Quick Reference

5.4Configuring Boot Actions

Embedded BIOS supports up to six different user-defined steps in the boot sequence. When the entire system has been initialized, POST executes these steps in order until an operating system successfully loads. In addition, other pre-boot features can be run before, after, or between operating system load attempts. The following actions can be used:

Drive A: - K:

Boot operating system from specified drive. If “Loader” is set to “BootRecord”

 

or “Unused”, then the standard boot record will be invoked, causing DOS,

 

Windows95/98, Windows NT, or other industry-standard operating systems to

 

load. If “Boot Method” is set to “Windows CE”, then the boot drive’s boot

 

record will not be used, and instead the BIOS will attempt to load and execute

 

the Windows CE Kernel file, NK.BIN, from the root directory of each boot

 

device.

Debugger

Launch the Integrated BIOS Debugger. To return to the boot process from the

 

debugger environment, type “G” at the debugger prompt and press ENTER.

MFGMODE

Initiate Manufacturing Mode, allowing the system to be configured remotely

 

via an RS232 connect to a host computer.

WindowsCE

Execute a ROM-resident copy of Windows CE, if available. This feature is not

 

applicable unless properly configured by the OEM in the BIOS adaptation.

DOS in ROM

Execute a ROM-resident copy of DOS, if available. This feature is not

 

applicable unless an XIP copy of DOS, such as Embedded DOS-ROM, has been

 

stored in the BIOS boot ROM. Copies of Embedded DOS-ROM may be

 

obtained from General Software.

None

No action; POST proceeds to the next activity in the sequence.

5.5Custom Configuration Setup Screen

The system’s hardware-specific features are configured with the Custom Setup Screen

(Figure 5-4). All features are straightforward except for the Redirect Debugger I/O option, which is an extra embedded feature that allows the user to select whether the Integrated BIOS Debugger should use standard keyboard and video or RS232 console redirection for interaction with the user. If no video is available, the debugger is always redirected.

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Celeron™ Processor Development Kit Manual

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Contents Celeron Processor Development Kit ManualCeleron Processor Development Kit Manual Contents Hardware Reference Figures TablesPage Content Overview Text ConventionsTechnical Support Electronic Support SystemsProduct Literature Telephone Technical SupportRelated Documents Processor Assembly Features OverviewBaseboard Features Included HardwareSoftware Key Features General Software, IncBefore You Begin VGA MonitorSetting up the Evaluation Board Evaluation Board Jumpers and ConnectorsGetting Started Configuring the Bios Page Block Diagram Evaluation Board Block DiagramCeleron Processor System Operation2 82443BX Host Bridge/Controller 3 ITP System Bus Interface4 82371EB PCI to ISA/IDE Xcelerator PIIX4E PowerBoot ROM DramAGP Connector PCI ConnectorsISA Connectors IDE SupportInterrupt Map Post Code DebuggerClock Generation InterruptsMemory Map Memory MapSize Description Page Thermal Management Processor AssemblyPost Code Debugger ITP Debugger PortPCI Device Mapping ISA and PCI Expansion SlotsPCI Device Mapping Device Address Line PCI Device NumberPrimary Power Connector J11 Connector PinoutsATX Power Connector Pin Name FunctionUSB Connector Pinout J2 ITP Debugger ConnectorITP Connector Pin Assignment J2 on the Processor Assembly Stacked USBDB25 Parallel Port Connector Pinout J3 Mouse and Keyboard ConnectorsKeyboard and Mouse Connector Pinouts J1 on the Baseboard Pin Signal NamePCI IDE1 JP3 and IDE2 JP4 Connector IDE ConnectorSerial Port Connector Pinout J4 Serial PortsFloppy Drive Connector Diskette Drive Header Connector JP1PCI Slot Connector 10. PCI Slots J7, J8, J9ISA Slot Connector 11. ISA Slots J5, J612. AGP Slot J13 AGP ConnectorPin# Jumpers Enable Spread Spectrum Clocking J1413. Default Jumper Settings Clock Frequency Selection J15Push Button Switches Flash Bios VPP Select J21Flash Bios Boot Block Control J22 6 SMI# Source Control J23In-Circuit Bios Update Page Bios and Pre-Boot Features Power-On Self-Test PostBios Post Pre-Boot Environment Setup Screen System Basic Cmos Configuration ScreenConfiguring Drive Assignments Embedded Bios Basic Setup ScreenIDE0-IDE3 Drive Assignments Configuring IDE Drive TypesFile System Name Controller Master/Slave Configuring Boot Actions Custom Configuration Setup ScreenShadow Configuration Setup Screen Embedded Bios Custom Setup ScreenStandard Diagnostics Routines Setup Screen Start System Bios Debugger Setup ScreenManufacturing Mode Start RS232 Manufacturing Link Setup ScreenConsole Redirection Integrated Bios Debugger CE-Ready Windows CE LoaderIntegrated Bios Debugger Running Over a Remote Terminal Embedded Bios Post Codes Poststatusvideorom Poststatusbeforesetup Embedded Bios Beep Codes PostbeeprefreshPage PLD Code Listing PLD Code Listing Table B-1. Baseboard Bill of Materials Sheet 1 Reference Description Manufacturer Manufacturer P/NBios Flash Intel Table B-1. Baseboard Bill of Materials Sheet 2Table B-1. Baseboard Bill of Materials Sheet 3 Reference Description ManufacturerTable B-1. Baseboard Bill of Materials Sheet 4 SOIC20,SO20WReference Descriptions Manufacturer Manufacturer P/N ECJ-1VB1C104KERJ-6GEYJ472V Schematics Evaluation Platform System Electronic s Board PCI BUS Mini PCI Connector This Drawing Contains Information Which has not Socket DIMM1 DIMM2 This Drawing Contains Information Which has not This Drawing Contains Information Which Hasnot PCI Slot PCI Slot Been Verified for Manufacturing AS AN END Seru Title Been Verified for Manufacturing AS AN Enduser Title USB Secondary IDE Connector ISA/Host USB Connectors ISA Slots COM0/COM1 Port Speaker Header Unused Gates CeleronTM Processor Ppga Daughter Board ITP Pin Socket PRODUCT. Intel is not Responsible for GTL+ Termination RESISTORS-BX GTL+ Termination RESISTORS-CPU 82443BX BX Strapping Options Mounting Holes Thermal Sensor TIE Directly to Ground Plane Index Index-2