Intel 273246-002 manual Poststatusvideorom

Page 53

BIOS Quick Reference

POST_STATUS_VIDEOROM

2ch

Passing control to video ROM.

POST_STATUS_POSTVIDEO

2dh

Control returned from video ROM.

POST_STATUS_CHECKEGAVGA

2eh

Check for EGA/VGA adapter.

POST_STATUS_TESTVIDEOMEMORY

2fh

No EGA/VGA found, test video memory.

POST_STATUS_RETRACE

30h

Scan for video retrace signal.

POST_STATUS_ALTDISPLAY

31h

Primary retrace failed.

POST_STATUS_ALTRETRACE

32h

Alternate found.

POST_STATUS_VRFYSWADAPTER

33h

Verify video switches.

POST_STATUS_SETDISPMODE

34h

Establish display mode.

POST_STATUS_CHECKSEG40A

35h

Initialize ROM BIOS data area.

POST_STATUS_SETCURSOR

36h

Set cursor for power-on msg.

POST_STATUS_PWRONDISPLAY

37h

Display power-on message.

POST_STATUS_SAVECURSOR

38h

Save cursor position.

POST_STATUS_BIOSIDENT

39h

Display BIOS identification string.

POST_STATUS_HITDEL

3ah

Display "Hit <DEL> to ..." message.

POST_STATUS_VIRTUAL

40h

Prepare protected mode test.

POST_STATUS_DESCR

41h

Prepare descriptor tables.

POST_STATUS_ENTERVM

42h

Enter virtual mode for memory test.

POST_STATUS_ENABINT

43h

Enable interrupts for diagnostics mode.

POST_STATUS_CHECKWRAP1

44h

Initialize data for memory wrap test.

POST_STATUS_CHECKWRAP2

45h

Test for wrap, find total memory size.

POST_STATUS_HIGHPATTERNS

46h

Write extended memory test patterns.

POST_STATUS_LOWPATTERNS

47h

Write conventional memory test patterns.

POST_STATUS_FINDLOWMEM

48h

Find low memory size from patterns.

POST_STATUS_FINDHIMEM

49h

Find high memory size from patterns.

POST_STATUS_CHECKSEG40B

4ah

Verify ROM BIOS data area again.

POST_STATUS_CHECKDEL

4bh

Check for <DEL> pressed.

POST_STATUS_CLREXTMEM

4ch

Clear extended memory for soft reset.

POST_STATUS_SAVEMEMSIZE

4dh

Save memory size.

POST_STATUS_COLD64TEST

4eh

Cold boot: Display 1st 64KB memtest.

POST_STATUS_COLDLOWTEST

4fh

Cold boot: Test all of low memory.

POST_STATUS_ADJUSTLOW

50h

Adjust memory size for EBDA usage.

POST_STATUS_COLDHITEST

51h

Cold boot: Test high memory.

POST_STATUS_REALMODETEST

52h

Prepare for shutdown to real mode.

POST_STATUS_ENTERREAL

53h

Return to real mode.

POST_STATUS_SHUTDOWN

54h

Shutdown successful.

POST_STATUS_DISABA20

55h

Disable A20 line.

POST_STATUS_CHECKSEG40C

56h

Check ROM BIOS data area again.

POST_STATUS_CHECKSEG40D

57h

Check ROM BIOS data area again.

POST_STATUS_CLRHITDEL

58h

Clear "Hit <DEL>" message.

POST_STATUS_TESTDMAPAGE

59h

Test DMA page register file.

POST_STATUS_VRFYDISPMEM

60h

Verify from display memory.

POST_STATUS_TESTDMA0BASE

61h

Test DMA0 base register.

POST_STATUS_TESTDMA1BASE

62h

Test DMA1 base register.

POST_STATUS_CHECKSEG40E

63h

Checking ROM BIOS data area again.

POST_STATUS_CHECKSEG40F

64h

Checking ROM BIOS data area again.

POST_STATUS_PROGDMA

65h

Program DMA controllers.

POST_STATUS_INITINTCTRL

66h

Initialize PICs.

POST_STATUS_STARTKBDTEST

67h

Start keyboard test.

POST_STATUS_KBDRESET

80h

Issue KB reset command.

POST_STATUS_CHECKSTUCKKEYS

81h

Check for stuck keys.

POST_STATUS_INITCIRCBUFFER

82h

Initialize circular buffer.

POST_STATUS_CHECKLOCKEDKEYS

83h

Check for locked keys.

POST_STATUS_MEMSIZEMISMATCH

84h

Check for memory size mismatch.

POST_STATUS_PASSWORD

85h

Check for password or bypass setup.

Celeron™ Processor Development Kit Manual

5-13

Image 53
Contents Development Kit Manual Celeron ProcessorCeleron Processor Development Kit Manual Contents Hardware Reference Tables FiguresPage Text Conventions Content OverviewElectronic Support Systems Technical SupportTelephone Technical Support Product LiteratureRelated Documents Overview Processor Assembly FeaturesIncluded Hardware Baseboard FeaturesGeneral Software, Inc Software Key FeaturesVGA Monitor Before You BeginEvaluation Board Jumpers and Connectors Setting up the Evaluation BoardGetting Started Configuring the Bios Page Evaluation Board Block Diagram Block Diagram2 82443BX Host Bridge/Controller System OperationCeleron Processor System Bus Interface 3 ITPBoot ROM Power4 82371EB PCI to ISA/IDE Xcelerator PIIX4E DramISA Connectors PCI ConnectorsAGP Connector IDE SupportClock Generation Post Code DebuggerInterrupt Map InterruptsSize Description Memory MapMemory Map Page Post Code Debugger Processor AssemblyThermal Management ITP Debugger PortPCI Device Mapping ISA and PCI Expansion SlotsPCI Device Mapping Device Address Line PCI Device NumberATX Power Connector Connector PinoutsPrimary Power Connector J11 Pin Name FunctionITP Connector Pin Assignment J2 on the Processor Assembly ITP Debugger ConnectorUSB Connector Pinout J2 Stacked USBKeyboard and Mouse Connector Pinouts J1 on the Baseboard Mouse and Keyboard ConnectorsDB25 Parallel Port Connector Pinout J3 Pin Signal NameSerial Port Connector Pinout J4 IDE ConnectorPCI IDE1 JP3 and IDE2 JP4 Connector Serial PortsDiskette Drive Header Connector JP1 Floppy Drive Connector10. PCI Slots J7, J8, J9 PCI Slot Connector11. ISA Slots J5, J6 ISA Slot ConnectorPin# AGP Connector12. AGP Slot J13 13. Default Jumper Settings Enable Spread Spectrum Clocking J14Jumpers Clock Frequency Selection J15Flash Bios Boot Block Control J22 Flash Bios VPP Select J21Push Button Switches 6 SMI# Source Control J23In-Circuit Bios Update Page Power-On Self-Test Post Bios and Pre-Boot FeaturesBios Post Pre-Boot Environment Basic Cmos Configuration Screen Setup Screen SystemEmbedded Bios Basic Setup Screen Configuring Drive AssignmentsFile System Name Controller Master/Slave Configuring IDE Drive TypesIDE0-IDE3 Drive Assignments Custom Configuration Setup Screen Configuring Boot ActionsEmbedded Bios Custom Setup Screen Shadow Configuration Setup ScreenStart System Bios Debugger Setup Screen Standard Diagnostics Routines Setup ScreenConsole Redirection Start RS232 Manufacturing Link Setup ScreenManufacturing Mode CE-Ready Windows CE Loader Integrated Bios DebuggerIntegrated Bios Debugger Running Over a Remote Terminal Embedded Bios Post Codes Poststatusvideorom Poststatusbeforesetup Postbeeprefresh Embedded Bios Beep CodesPage PLD Code Listing PLD Code Listing Reference Description Manufacturer Manufacturer P/N Table B-1. Baseboard Bill of Materials Sheet 1Table B-1. Baseboard Bill of Materials Sheet 2 Bios Flash IntelReference Description Manufacturer Table B-1. Baseboard Bill of Materials Sheet 3SOIC20,SO20W Table B-1. Baseboard Bill of Materials Sheet 4ECJ-1VB1C104K Reference Descriptions Manufacturer Manufacturer P/NERJ-6GEYJ472V Schematics Evaluation Platform System Electronic s Board PCI BUS Mini PCI Connector This Drawing Contains Information Which has not Socket DIMM1 DIMM2 This Drawing Contains Information Which has not This Drawing Contains Information Which Hasnot PCI Slot PCI Slot Been Verified for Manufacturing AS AN END Seru Title Been Verified for Manufacturing AS AN Enduser Title USB Secondary IDE Connector ISA/Host USB Connectors ISA Slots COM0/COM1 Port Speaker Header Unused Gates CeleronTM Processor Ppga Daughter Board ITP Pin Socket PRODUCT. Intel is not Responsible for GTL+ Termination RESISTORS-BX GTL+ Termination RESISTORS-CPU 82443BX BX Strapping Options Mounting Holes Thermal Sensor TIE Directly to Ground Plane Index Index-2