Intel 273246-002 manual Configuring IDE Drive Types, IDE0-IDE3 Drive Assignments

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BIOS Quick Reference

5.3.3Configuring IDE Drive Types

If true IDE disk file systems (and not their emulators, such as ROM, RAM, or flash disks) are mapped to drive letters, then the IDE drives themselves must be configured in this section. The following table shows the drive assignments for Ide0-Ide3:

Table 5-1. IDE0-IDE3 Drive Assignments

File System Name

Controller

Master/Slave

 

 

 

Ide0

Primary (1f0h)

Master

 

 

 

Ide1

Primary (1f0h)

Slave

 

 

 

Ide2

Secondary (170h)

Master

 

 

 

Ide3

Secondary (170h)

Slave

 

 

 

To use the primary master IDE drive in your system (the typical case), just configure Ide0 in this section, and map Ide0 to drive C: in the Configuring Drive Assignments section.

The IDE Drive Types section lets you select the type for each of the four IDE drives: None, User, Physical, LBA, or CHS.

User

This type allows the user to select the maximum cylinders, heads, and sectors

 

per track associated with the IDE drive. This method is now rarely used since

 

LBA is now in common use.

Physical

This type instructs the BIOS to query the drive’s geometry from the controller

 

on each POST. No translation on the drive’s geometry is performed, so this type

 

is limited to drives of 512 Mbytes or less. Commonly, this is used with

 

embedded ATA PC Cards.

LBA

This type instructs the BIOS to query the drive’s geometry from the controller

 

on each POST, but then translate the geometry according to the industry-

 

standard LBA convention. This supports up to 16-Gbyte drives. Use this method

 

for all new drives.

CHS

This type instructs the BIOS to query the drive’s geometry from the controller

 

on each POST, but then translate the geometry according to the Phoenix CHS

 

convention. Using this type on a drive previously formatted with LBA or

 

Physical geometry might show data as being missing or corrupted.

Celeron™ Processor Development Kit Manual

5-5

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Contents Development Kit Manual Celeron ProcessorCeleron Processor Development Kit Manual Contents Hardware Reference Tables FiguresPage Text Conventions Content OverviewElectronic Support Systems Technical SupportTelephone Technical Support Product LiteratureRelated Documents Overview Processor Assembly FeaturesIncluded Hardware Baseboard FeaturesGeneral Software, Inc Software Key FeaturesVGA Monitor Before You BeginEvaluation Board Jumpers and Connectors Setting up the Evaluation BoardGetting Started Configuring the Bios Page Evaluation Board Block Diagram Block DiagramSystem Operation Celeron Processor2 82443BX Host Bridge/Controller System Bus Interface 3 ITPBoot ROM Power4 82371EB PCI to ISA/IDE Xcelerator PIIX4E DramISA Connectors PCI ConnectorsAGP Connector IDE SupportClock Generation Post Code DebuggerInterrupt Map InterruptsMemory Map Memory MapSize Description Page Post Code Debugger Processor AssemblyThermal Management ITP Debugger PortPCI Device Mapping ISA and PCI Expansion SlotsPCI Device Mapping Device Address Line PCI Device NumberATX Power Connector Connector PinoutsPrimary Power Connector J11 Pin Name FunctionITP Connector Pin Assignment J2 on the Processor Assembly ITP Debugger ConnectorUSB Connector Pinout J2 Stacked USBKeyboard and Mouse Connector Pinouts J1 on the Baseboard Mouse and Keyboard ConnectorsDB25 Parallel Port Connector Pinout J3 Pin Signal NameSerial Port Connector Pinout J4 IDE ConnectorPCI IDE1 JP3 and IDE2 JP4 Connector Serial PortsDiskette Drive Header Connector JP1 Floppy Drive Connector10. PCI Slots J7, J8, J9 PCI Slot Connector11. ISA Slots J5, J6 ISA Slot ConnectorAGP Connector 12. AGP Slot J13Pin# 13. Default Jumper Settings Enable Spread Spectrum Clocking J14Jumpers Clock Frequency Selection J15Flash Bios Boot Block Control J22 Flash Bios VPP Select J21Push Button Switches 6 SMI# Source Control J23In-Circuit Bios Update Page Power-On Self-Test Post Bios and Pre-Boot FeaturesBios Post Pre-Boot Environment Basic Cmos Configuration Screen Setup Screen SystemEmbedded Bios Basic Setup Screen Configuring Drive AssignmentsConfiguring IDE Drive Types IDE0-IDE3 Drive AssignmentsFile System Name Controller Master/Slave Custom Configuration Setup Screen Configuring Boot ActionsEmbedded Bios Custom Setup Screen Shadow Configuration Setup ScreenStart System Bios Debugger Setup Screen Standard Diagnostics Routines Setup ScreenStart RS232 Manufacturing Link Setup Screen Manufacturing ModeConsole Redirection CE-Ready Windows CE Loader Integrated Bios DebuggerIntegrated Bios Debugger Running Over a Remote Terminal Embedded Bios Post Codes Poststatusvideorom Poststatusbeforesetup Postbeeprefresh Embedded Bios Beep CodesPage PLD Code Listing PLD Code Listing Reference Description Manufacturer Manufacturer P/N Table B-1. Baseboard Bill of Materials Sheet 1Table B-1. Baseboard Bill of Materials Sheet 2 Bios Flash IntelReference Description Manufacturer Table B-1. Baseboard Bill of Materials Sheet 3SOIC20,SO20W Table B-1. Baseboard Bill of Materials Sheet 4ECJ-1VB1C104K Reference Descriptions Manufacturer Manufacturer P/NERJ-6GEYJ472V Schematics Evaluation Platform System Electronic s Board PCI BUS Mini PCI Connector This Drawing Contains Information Which has not Socket DIMM1 DIMM2 This Drawing Contains Information Which has not This Drawing Contains Information Which Hasnot PCI Slot PCI Slot Been Verified for Manufacturing AS AN END Seru Title Been Verified for Manufacturing AS AN Enduser Title USB Secondary IDE Connector ISA/Host USB Connectors ISA Slots COM0/COM1 Port Speaker Header Unused Gates CeleronTM Processor Ppga Daughter Board ITP Pin Socket PRODUCT. Intel is not Responsible for GTL+ Termination RESISTORS-BX GTL+ Termination RESISTORS-CPU 82443BX BX Strapping Options Mounting Holes Thermal Sensor TIE Directly to Ground Plane Index Index-2