Intel 273246-002 manual Socket

4

A

B

C

D

E

V 3 _

3

C 1 0 5

C 1 5 5

C 2 2 6

C 1 9 9

C 1 7 5

C 2 2 8

C 2 0 2

C 2 0 1

C 2 0 7

C 2 0 4

4 7 u F

4 7 u F

0 . 1uF

0 . 1uF

0 . 1uF

0 . 1uF

0 . 01uF

0 . 01uF

0 . 01uF

0 . 01uF

Socket 0

4

3

2

1

	4,6,7		MECC[7:0]
	4,6		MAA[13:0]
	4,6,7		MD[63:0]
					J18
			M D 0	A 0 1	GND	GND	B 8 5	M D 3 2
				A 0 2			B 8 6
					D Q 0	D Q 3 2
			M D 1	A 0 3			B 8 7	M D 3 3
					D Q 1	D Q 3 3
			M D 2	A 0 4			B 8 8	M D 3 4
					D Q 2	D Q 3 4
			M D 3	A 0 5			B 8 9	M D 3 5
					D Q 3	D Q 3 5
				A 0 6			B 9 0
			M D 4		V 3 _ 3	V 3 _ 3		M D 3 6
				A 0 7			B 9 1
					D Q 4	D Q 3 6
			M D 5	A 0 8			B 9 2	M D 3 7
			M D 6	A 0 9	D Q 5	D Q 3 7	B 9 3	M D 3 8
					D Q 6	D Q 3 8
			M D 7	A 1 0			B 9 4	M D 3 9
					D Q 7	D Q 3 9
			M D 8	A 1 1	D Q 8	D Q 4 0	B 9 5	M D 4 0
				A 1 2			B 9 6
			M D 9		GND	GND		M D 4 1
				A 1 3			B 9 7
					D Q 9	D Q 4 1
			M D 1 0	A 1 4			B 9 8	M D 4 2
					D Q 1 0	D Q 4 2
			M D 1 1	A 1 5			B 9 9	M D 4 3
					D Q 1 1	D Q 4 3
			M D 1 2	A 1 6			B 1 0 0	M D 4 4
			M D 1 3	A 1 7	D Q 1 2	D Q 4 4	B 1 0 1	M D 4 5
					D Q 1 3	D Q 4 5
				A 1 8			B 1 0 2
			M D 1 4		V 3 _ 3	V 3 _ 3		M D 4 6
				A 1 9			B 1 0 3
					D Q 1 4	D Q 4 6
			M D 1 5	A 2 0			B 1 0 4	M D 4 7
					D Q 1 5	D Q 4 7
			MECC0	A 2 1			B 1 0 5	MECC4
					CB0	CB4
			MECC1	A 2 2			B 1 0 6	MECC5
					CB1	CB5
				A 2 3			B 1 0 7
					GND	GND
				A 2 4			B 1 0 8
					NC	NC
				A 2 5			B 1 0 9
					NC	NC
				A 2 6			B 1 1 0
					V 3 _ 3	V 3 _ 3
				A 2 7			B 1 1 1			SCASA#	4,7
		4,7	W E _ A #		W E 0	/CAS
				A 2 8			B 1 1 2
		4,6,7	D Q M A 0		D Q M B 0	D Q M B 4				D Q M A 4	4,6,7
				A 2 9			B 1 1 3
		4,6	D Q M A 1		D Q M B 1	D Q M B 5				D Q M A 5	4,6
				A 3 0			B 1 1 4
		4	CS _ A0#		/S0	/S1				CS _ A1#	4
				A 3 1			B 1 1 5
					DU	/RAS				SRASA#	4,7
				A 3 2			B 1 1 6
			M A A 0		GND	GND		M A A 1
				A 3 3			B 1 1 7
					A 0	A 1
			M A A 2	A 3 4			B 1 1 8	M A A 3
					A 2	A 3
			M A A 4	A 3 5			B 1 1 9	M A A 5
					A 4	A 5
			M A A 6	A 3 6			B 1 2 0	M A A 7
					A 6	A 7
			M A A 8	A 3 7			B 1 2 1	M A A 9
			M A A 1 0	A 3 8	A 8	A 9	B 1 2 2	M A A 1 1
					A10(AP)	BA0
			M A A 1 2	A 3 9			B 1 2 3	M A A 1 3
					BA1	A 1 1
				A 4 0			B 1 2 4
					V 3 _ 3	V 3 _ 3
				A 4 1	V 3 _ 3	CK1	B 1 2 5	M A A 1 2		SDCLK1	8
				A 4 2			B 1 2 6
		8	SDCLK0		CK0	A 1 2
				A 4 3			B 1 2 7
					GND	GND
				A 4 4			B 1 2 8			CKE0	4
					DU	CKE0
				A 4 5			B 1 2 9
		4	CS _ B0#		/S2	/S3				CS _ B1#	4
				A 4 6			B 1 3 0
		4,6,7	D Q M A 2		D Q M B 2	D Q M B 6				D Q M A 6	4,6,7
				A 4 7			B 1 3 1
		4,6,7	D Q M A 3		D Q B M 3	D Q M B 7				D Q M A 7	4,6,7
				A 4 8			B 1 3 2
					DU	A 1 3
				A 4 9			B 1 3 3
					V 3 _ 3	V 3 _ 3
				A 5 0			B 1 3 4
					NC	NC
				A 5 1			B 1 3 5
			MECC2		NC	NC		MECC6	R48
				A 5 2			B 1 3 6
					CB2	CB6
			MECC3	A 5 3			B 1 3 7	MECC7	0	V 3 _ 3
					CB3	CB7
				A 5 4			B 1 3 8
			M D 1 6		GND	GND		M D 4 8
				A 5 5			B 1 3 9
					D Q 1 6	D Q 4 8
			M D 1 7	A 5 6			B 1 4 0	M D 4 9		R52
					D Q 1 7	D Q 4 9
			M D 1 8	A 5 7			B 1 4 1	M D 5 0		0
					D Q 1 8	D Q 5 0
			M D 1 9	A 5 8			B 1 4 2	M D 5 1
					D Q 1 9	D Q 5 1
				A 5 9			B 1 4 3
			M D 2 0		V 3 _ 3	V 3 _ 3		M D 5 2
				A 6 0			B 1 4 4
					D Q 2 0	D Q 5 2
				A 6 1			B 1 4 5
					NC	NC
				A 6 2			B 1 4 6
					VREF (NC)	DU
				A 6 3			B 1 4 7
	4	CKE1			CKE1	REGE
				A 6 4			B 1 4 8
			M D 2 1		GND	GND		M D 5 3
				A 6 5			B 1 4 9
					D Q 2 1	D Q 5 3
			M D 2 2	A 6 6			B 1 5 0	M D 5 4
					D Q 2 2	D Q 5 4
			M D 2 3	A 6 7			B 1 5 1	M D 5 5
					D Q 2 3	D Q 5 5
				A 6 8			B 1 5 2
			M D 2 4		GND	GND		M D 5 6
				A 6 9			B 1 5 3
					D Q 2 4	D Q 5 6
			M D 2 5	A 7 0			B 1 5 4	M D 5 7
					D Q 2 5	D Q 5 7
			M D 2 6	A 7 1			B 1 5 5	M D 5 8
					D Q 2 6	D Q 5 8
			M D 2 7	A 7 2			B 1 5 6	M D 5 9
					D Q 2 7	D Q 5 9
				A 7 3			B 1 5 7
			M D 2 8		V 3 _ 3	V 3 _ 3		M D 6 0
				A 7 4			B 1 5 8
					D Q 2 8	D Q 6 0
			M D 2 9	A 7 5			B 1 5 9	M D 6 1
					D Q 2 9	D Q 6 1
			M D 3 0	A 7 6			B 1 6 0	M D 6 2
					D Q 3 0	D Q 6 2
			M D 3 1	A 7 7			B 1 6 1	M D 6 3
					D Q 3 1	D Q 6 3
				A 7 8			B 1 6 2
					GND	GND
				A 7 9			B 1 6 3			SDCLK3	8
	8	SDCLK2			CK2	CK3
				A 8 0			B 1 6 4
					NC	NC
				A 8 1			B 1 6 5
					WP	SA0
				A 8 2			B 1 6 6
4,6,7,8,9,14	S M B D A T A				SDA	SA1
				A 8 3			B 1 6 7
4,6,7,8,9,14	SMBCLK				SCL	SA2
				A 8 4			B 1 6 8
					V 3 _ 3	V 3 _ 3		Slave address 10100000b

SDRAM DIMM

THIS DRAWING CONTAINS INFORMATION WHICH HAS NOT

BEEN VERIFIED FOR MANUFACTURING AS AN ENDUSER

PRODUCT. INTEL IS NOT RESPONSIBLE FORTHE

MISUSE OF THIS INFORMATIO.

Title	DIMM0
Size	Document Number					Rev
C	{Doc}					D
Date:	Thursday, February 25, 1999	Sheet	5	of	2 2

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