Texas Instruments TCM4300 Mcds, MTS1, Mclkin, Mcrw, MTS0, Mwbdfint, OUT1, Paen, Pwrcont, Rbias

Page 14

1.4Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

 

 

 

 

 

 

MCDS

48

I

Microcontroller data strobe. MCDS is configured by the signals present on MTS0 and

 

 

 

MTS1.

 

 

 

 

MCLKIN

64

I

Master clock input. The MCLKIN frequency input requirement is 38.88 MHz ± 100 ppm.

 

 

 

A crystal can be connected between MCLKIN and XTAL to provide an oscillator circuit.

 

 

 

As an alternative, XTAL can be left open and an external TTL /CMOS-level clock signal

 

 

 

can be connected to MCLKIN.

 

 

 

 

MCRW

47

I

Microcontroller read/write. Microcontroller read/write operations are selected in

 

 

 

accordance with the signals present on MTS0 and MTS1.

 

 

 

 

MTS0

36

I

Microcontroller type select configuration-control inputs. The interface is controlled by

 

 

 

MTS (1:0) as follows:

 

 

 

00 ± Intelmicrocontroller interface characteristics

MTS1

37

I

10 ± Mitsubishiand Motorolamicrocontroller 16-bit bus interface characteristics

01 ± Motorolamicrocontroller 8-bit bus characteristics

 

 

 

 

 

 

11 ± Reserved

 

 

 

 

MWBDFINT

50

O

Microcontroller interrupt request. A wide-band data-ready interrupt is output when the

 

 

 

WBD demodulator is in analog mode or when a frame interrupt is sent by the DSP in

 

 

 

digital mode. MWDBFINT can be active high or low according to the levels of the MTS0

 

 

 

and MTS1 signals.

 

 

 

 

OUT1

26

O

Output number 1. OUT1 provides a user-defined general purpose data or control signal.

 

 

 

 

PAEN

25

O

Power amplifier enable. PAEN can be used to enable the transmit power amplifier. This

 

 

 

signal is active high.

 

 

 

 

PWRCONT

16

O

Power amplifier (PA) power control. The PWRCONT DAC output can be used to control

 

 

 

the amount of power output from the PA.

 

 

 

 

RBIAS

99

I

Input for bias current-setting resistor. To achieve correct bias voltage, a 100-kΩ, 1%

 

 

 

tolerance resistor connected between RBIAS and AVSS is recommended.

REFCAP

100

I

Reference decoupling capacitor. For proper decoupling, It is recommended that a

 

 

 

3.3 μF capacitor in parallel with a 470-pF capacitor be connected between REFCAP and

 

 

 

ground.

 

 

 

 

RSINL

59

I

Reset input low. An active low applied to RSINL resets the TCM4300.

 

 

 

 

RSSI

2

I

Received signal strength indicator. RSSI samples received signal strength.

 

 

 

 

RSOUTH

60

O

Reset out high. An active high is output from RSOUTH for 10 ms after the TCM4300 is

 

 

 

powered up.

 

 

 

 

RSOUTL

61

O

Reset out low. An active low is output from RSOUTL for 10 ms after the TCM4300 is

 

 

 

powered up.

 

 

 

 

RXIN

8

I

Negative receive input. The in-phase differential negative baseband received signal is

 

 

 

applied to RXIN.

 

 

 

 

RXIP

9

I

Positive receive input. The in-phase differential positive baseband received signal is

 

 

 

applied to RXIP.

 

 

 

 

RXQN

5

I

Negative receive input. The quadrature negative baseband received signal is applied

 

 

 

to RXQN.

 

 

 

 

RXQP

6

I

Positive receive input. The quadrature differential positive baseband received signal is

 

 

 

applied to RXQP.

Intel is a trademark of Intel Corporation.

Mitsubishi is a trademark of Mitsubishi Inc.

Motorola is a trademark of Motorola, Inc.

1±6

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Contents Data Manual SLWS010F TCM4300 Data Manual Important Notice Contents Mechanical Data ±1 List of Illustrations List of Tables Features IntroductionTCM4300 Functional Block Diagram VSS Pin AssignmentsPZ Package TOP View FmrxenTerminal Functions Terminal Description NameDvdd DsprwDspstrbl DvssMclkin McdsMTS1 McrwSynclk ScenSint SyndtaPackage Power Rating Above TA = 25CDissipation Rating Table Derating FactorRecommended Operating Conditions Power ConsumptionReference Characteristics Function MIN TYP² MAX Unit Terminal ImpedanceRXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Parameter Test Conditions MIN TYP MAX UnitParameter MIN TYP MAX Unit Transmit I and Q Channel OutputsAuxiliary D/A Converters Auxiliary D/A Converters Slope Lcdcontr RSSI/Battery A/D ConverterAuxiliary D/A Converters Slope AGC, AFC, Pwrcont Nominal LSB Nominal Output VoltageTransmit TX Channel Frequency Response Digital Mode Transmit TX Channel Frequency Response Analog Mode Page VOH VOL Mclkout Timing Requirements see ±1 and NoteMclkout Mcrw Parameter Alternate MIN MAX UnitMcds MCA4±MCA0 MCD7±MCD0 Mccsh MccslParameter Alternate MIN MAX Unit Symbol MCA4±MCA0MCA4±MCA0 MCD7±MCD0 Twdho Motorola 16-Bit Read Cycle, MTS 10 = MCA0±MCA4 MCD0±MCD7 Mccsh MccslMCA0±MCA4 Mcrw MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl10% ThR / W ThWA Dsprw DspcslDspstrbl Dspa Dspd±11. TCM4300 to DSP Interface Write Cycle ±12 Mode Fmvox Iqrxen Fmrxen ±1. TCM4300 Receive Channel Control SignalsControl Signal Analog Mode Digital Mode Data Transfer±2. RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Transmit Section Modulation error percentage +100 s % ±5. Transmit TX I and Q Channel Outputs±7. Transmit TX Channel Frequency Response Analog Mode Transmit Burst Operation Digital Mode±6. Transmit TX Channel Frequency Response Digital Mode ±1. Power Ramp-Up/Ramp-Down TIming Diagram Transmit I And Q Output Level Wide-Band Data Demodulator±9. Bits in Control Register WBDCtrl ±8. Typical Bit-Error-Rate Performance Wbdbw =Wide-band Data Interrupts Parameter Test Conditions MIN MAX Unit Mean CNRWide-band Data Demodulator General Information WBD±11. Auxiliary D /A Converters Slope AGC, AFC, Pwrcont Auxiliary DACs, LCD Contrast Converter±10. Auxiliary D/A Converters Timing And Clock Generation RSSI, Battery Monitor±13. RSSI/Battery A/D Converter ±12. Auxiliary D /A Converters Slope LcdcontrMicrocontroller Clock Clock GenerationSpeech-Codec Clock Generation Sample Interrupt SintPhase-Adjustment Strategy Mclken RCOMclkin Frequency Synthesizer Interface MSB/LSB First Clkpol Numclks LowvalHighval Syndta±14. Synthesizer Control Fields Name DescriptionName Suggested External Application Reset Power Control Port15. External Power Control Signals Synclk Syndta SYNLE1 SYNLE0 SynrdyOUT1 Iqrxen Txen ModeWBD Wbdon Fmrxen ScenFifo a Fifo B Microcontroller-DSP CommunicationsDint Cint DSPMicrocontroller Register Map ±16. Microcontroller Register MapAddr Name Category Wide-Band Data/Control Register±17. Microcontroller Register Definitions ±18. WBDCtrl Register BIT Name Function Reset ValueMicrocontroller Status and Control Registers LDC D/A LCD Contrast±19. MStatCtrl Register Bits Lcden±21. DSP Register Definitions DSP Register Map±20. DSP Register Map Dspcsl TCM4300 Dsprw Dspstrbl Sint Cint Bdint Wide-Band Data RegistersBase Station Offset Register DSP Strb INTDSP Status and Control Registers ±22. DStatCtrl Register BitsInternal Reset State ResetPower-On Reset ±23. Power-On Reset Register Initialization±25. Microcontroller Interface Connections for Intel Mode Intel Microcontroller Mode Of Operation±24. Microcontroller Interface Configuration Microcontroller InterfaceMcrw Mcds Mitsubishi Microcontroller Mode of OperationMotorola Microcontroller Mode of Operation IRQ NMI DintCS3 ±32 Mechanical Data PZ S-PQFP-G100Important Notice
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