Texas Instruments TCM4300 manual Twdho

3.5TCM4300 to Microcontroller Interface Timing Requirements (Intel Write Cycle) (see Figure 3±5 and Note 3)

	PARAMETER	ALTERNATE	MIN MAX	UNIT
		SYMBOL
tsu(WA)	Setup time, write address MCA stable before falling edge	TWA(SU)	0	ns
	of strobe MCRW
th(WA)	Hold time, write address MCA stable after rising edge of	TWA(HO)	10	ns
	strobe MCRW
tsu(W)	Setup time, write data stable MCD before rising edge of	TWD(SU)	14	ns
	strobe MCRW
th(W)	Hold time, write data stable MCD after rising edge of	TWD(HO)	0	ns
	strobe MCRW
tw(WSTB) Pulse duration, write strobe pulse width low on MCRW		TWR(STB)	60	ns
tsu(CS)	Setup time, chip select MCCSH and MCCSL stable before	TCS(SU)	0	ns
	falling edge of strobe MCRW
th(CS)	Hold time, chip select MCCSH and MCCSL stable before	TCS(HO)	0	ns
	rising edge of strobe MCRW

NOTE 3: Timings are based upon Intel 8C186 (16 MHz).

MCDS
			tw(WSTB)
MCRW	90%	10%	10%

(see Note A)

90%

tsu(WA)		th(WA)
MCA4±MCA0
	tsu(W)	th(W)
MCD7±MCD0
90%		90%
MCCSH
tsu(CS)	th(CS)

MCCSL

10% 10%

NOTE A: Chip selection is defined as both MCCS and MCRW active.

Figure 3±5. Microcontroller Interface Timing Requirements

(Intel Configuration Write Cycle, MTS [1:0] = 00)

3±5