Texas Instruments TCM4300 Clkpol Numclks Lowval, Highval, MSB/LSB First, Syndta, SYNLE0, SYNLE2

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				CLKPOL	5
				NUMCLKS	5
				NUMCLKS	5
				LOWVAL	5	Control
				LOWVAL	5	Control
				HIGHVAL	5	Registers
				HIGHVAL	3
				SEL[2:0]	3
		Ready		SEL[2:0]
		Ready	MSB/LSB FIRST
		and	MSB/LSB FIRST
		and
		Timing Logic	SYNRDY To MStatCtrl Register
			SYNRDY To MStatCtrl Register
SYNDTA
	D			M		32-Bit Data	8	μ
	D			U		Register		C
SYNLE0	Q			U	32			Bus
				X				Bus
				X
	E	SEL 0			5
					5
	D					DMUX	MSB/LSB
SYNLE1	Q					DMUX	MSB/LSB
SYNLE1	Q						FIRST
	E	SEL 1	A	HIGHVAL
		S	A = B
	D	Q	B
SYNLE2	Q	R	A	LOWVAL
	E	SEL 2	A	LOWVAL
	E	SEL 2	A = B
			A = B	5
		CLKPOL	B	5
		CLKPOL

		Clock	A	NUMCLKS
SYNCLK		Clock	B ≤ A
SYNCLK		Circuit	B ≤ A
		Circuit		BIT CNT
			B	BIT CNT			303.75 KHz
				[0 . . . 31]			303.75 KHz
				[0 . . . 31]

Figure 4±6. Synthesizer Interface Circuit Block Diagram

4±16

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Contents Data Manual SLWS010F TCM4300 Data Manual Important Notice Contents Mechanical Data ±1 List of Illustrations List of Tables Introduction FeaturesTCM4300 Functional Block Diagram Fmrxen Pin AssignmentsPZ Package TOP View VSSTerminal Description Name Terminal FunctionsDvss DsprwDspstrbl DvddMcrw McdsMTS1 MclkinSyndta ScenSint SynclkDerating Factor Power Rating Above TA = 25CDissipation Rating Table PackagePower Consumption Reference CharacteristicsRecommended Operating Conditions Parameter Test Conditions MIN TYP MAX Unit Terminal ImpedanceRXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Function MIN TYP² MAX UnitTransmit I and Q Channel Outputs Auxiliary D/A ConvertersParameter MIN TYP MAX Unit Nominal LSB Nominal Output Voltage RSSI/Battery A/D ConverterAuxiliary D/A Converters Slope AGC, AFC, Pwrcont Auxiliary D/A Converters Slope LcdcontrTransmit TX Channel Frequency Response Digital Mode Transmit TX Channel Frequency Response Analog Mode Page Mclkout Timing Requirements see ±1 and Note MclkoutVOH VOL MCA4±MCA0 MCD7±MCD0 Mccsh Mccsl Parameter Alternate MIN MAX UnitMcds McrwMCA4±MCA0 Parameter Alternate MIN MAX Unit SymbolMCA4±MCA0 MCD7±MCD0 Twdho MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl Motorola 16-Bit Read Cycle, MTS 10 =MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl Mcrw MCA0±MCA410% ThR / W ThWA Dspa Dspd DspcslDspstrbl Dsprw±11. TCM4300 to DSP Interface Write Cycle ±12 Data Transfer ±1. TCM4300 Receive Channel Control SignalsControl Signal Analog Mode Digital Mode Mode Fmvox Iqrxen Fmrxen±2. RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Transmit Section ±5. Transmit TX I and Q Channel Outputs Modulation error percentage +100 s %Transmit Burst Operation Digital Mode ±6. Transmit TX Channel Frequency Response Digital Mode±7. Transmit TX Channel Frequency Response Analog Mode ±1. Power Ramp-Up/Ramp-Down TIming Diagram Wide-Band Data Demodulator Transmit I And Q Output LevelParameter Test Conditions MIN MAX Unit Mean CNR ±8. Typical Bit-Error-Rate Performance Wbdbw =Wide-band Data Interrupts ±9. Bits in Control Register WBDCtrlWBD Wide-band Data Demodulator General InformationAuxiliary DACs, LCD Contrast Converter ±10. Auxiliary D/A Converters±11. Auxiliary D /A Converters Slope AGC, AFC, Pwrcont ±12. Auxiliary D /A Converters Slope Lcdcontr RSSI, Battery Monitor±13. RSSI/Battery A/D Converter Timing And Clock GenerationSample Interrupt Sint Clock GenerationSpeech-Codec Clock Generation Microcontroller ClockPhase-Adjustment Strategy RCO MclkinMclken Frequency Synthesizer Interface Syndta Clkpol Numclks LowvalHighval MSB/LSB FirstName Description ±14. Synthesizer Control FieldsSynclk Syndta SYNLE1 SYNLE0 Synrdy Power Control Port15. External Power Control Signals Name Suggested External Application ResetFmrxen Scen Iqrxen Txen ModeWBD Wbdon OUT1Cint DSP Microcontroller-DSP CommunicationsDint Fifo a Fifo B±16. Microcontroller Register Map Microcontroller Register MapWide-Band Data/Control Register ±17. Microcontroller Register DefinitionsAddr Name Category BIT Name Function Reset Value Microcontroller Status and Control Registers±18. WBDCtrl Register Lcden LCD Contrast±19. MStatCtrl Register Bits LDC D/ADSP Register Map ±20. DSP Register Map±21. DSP Register Definitions DSP Strb INT Wide-Band Data RegistersBase Station Offset Register Dspcsl TCM4300 Dsprw Dspstrbl Sint Cint Bdint±22. DStatCtrl Register Bits DSP Status and Control Registers±23. Power-On Reset Register Initialization ResetPower-On Reset Internal Reset StateMicrocontroller Interface Intel Microcontroller Mode Of Operation±24. Microcontroller Interface Configuration ±25. Microcontroller Interface Connections for Intel ModeIRQ NMI Dint Mitsubishi Microcontroller Mode of OperationMotorola Microcontroller Mode of Operation Mcrw McdsCS3 ±32 PZ S-PQFP-G100 Mechanical DataImportant Notice

CLKPOL

NUMCLKS

LOWVAL

HIGHVAL

MSB/LSB FIRST

SYNDTA

SYNLE0

SEL 0

DMUX

MSB/LSB

SYNLE1

FIRST

SYNLE2

SEL 2

CLKPOL

NUMCLKS

SYNCLK

BIT CNT

Figure 4±6. Synthesizer Interface Circuit Block Diagram