Texas Instruments TCM4300 manual Modulation error percentage +100 s %

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square-root raised-cosine (SQRC) shaping filter with a roll-off rate of α = 0.35 and converted to sampled analog form by two 9-bit digital-to-analog converters (DACs). The output of the DAC is then filtered by a continuous-time resistance-capacitance (RC) filter.

The TCM4300 generates a power amplifier (PA) control signal, PAEN, to enable the power supply for the PA. The start and stop times of the TDM burst are controlled by writing to a single bit, TXGO, in the DSP DStatCtrl register.

In the analog mode (MODE = 0), the DSP writes 8-bit I and Q samples into the TXI and TXQ data registers at a 40-ksps rate. These writes are timed by the SINT interrupt signal. The samples are fed to a low-pass filter before D/A conversion. In the transmit analog mode, PAEN is always set to 1.

The transmit section provides differential I and Q outputs (see Table 4-5) for both analog and digital modes. The differential dc offset for the TXI and TXQ outputs can be independently adjusted using the transmit offset registers.

Table 4±5. Transmit (TX) I and Q Channel Outputs

PARAMETER

 

MIN

TYP

MAX

UNIT

 

 

 

 

 

 

Peak output voltage full scale, centered at VCM

Differential

 

2.24

 

Vp

 

 

 

 

Single ended

 

1.12

 

 

 

 

 

 

 

 

 

 

 

Nominal output-level (constellation radius) centered at

Differential

 

1.5

 

V

VCM

Single ended

 

0.75

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low-level drift

 

 

± 200

 

PPM/°C

 

 

 

 

 

 

Transmit error vector magnitude (EVM)

 

 

3%

4%

 

 

 

 

 

 

 

Resolution

 

 

8

 

bits

 

 

 

 

 

 

S/(N+D) ratio at differential outputs

 

48

52

 

dB

 

 

 

 

 

 

Gain error (I or Q channel)

 

 

± 8%

± 12%

 

 

 

 

 

 

 

Gain mismatch between I and Q

 

 

 

± 0.3

dB

 

 

 

 

 

 

Gain sampling mismatch between I and Q

 

 

20

 

ns

 

 

 

 

 

 

Zero code error differential

 

 

 

± 80

mV

 

 

 

 

 

 

Zero code error, each output, with respect to VCM

 

 

 

± 80

mV

 

 

 

 

 

Zero code error, I to Q, with respect to other channel (differential or

 

 

± 10

mV

single ended)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Load impedance, between P and N terminals

 

10

 

 

kΩ

 

 

 

 

 

 

Transmit offset DACs I and Q resolution

 

 

6

 

bits

 

 

 

 

 

 

Transmit offset DACs I and Q average step size

 

2.9

3.4

3.9

mV

 

 

 

 

 

 

Transmit offset DACs I and Q full-scale positive output

 

 

105.4

 

mV

 

 

 

 

 

 

Transmit offset DACs I and Q full-scale negative output

 

 

± 108.8

 

mV

 

 

 

 

 

 

Transmit offset DACs differential nonlinearity

 

 

 

± 1.1

LSB

 

 

 

 

 

 

Transmit offset DACs integral nonlinearity

 

 

 

± 1.1

LSB

 

 

 

 

 

 

Modulation Error: In the digital mode, during the transmit burst, the complex output of the transmitter circuits

consists of an ideal output s = I ideal + jQideal + error e = ei + jeq. In Table 4-5, the modulation error vector magnitude (EVM) is defined as the peak value of the magnitude of e relative to the ideal output:

e

Modulation error percentage +100 s %

Table 4±6 and Table 4±7 show the frequency response of the transmit section for digital and analog mode, respectively.

4±4

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Contents Data Manual SLWS010F TCM4300 Data Manual Important Notice Contents Mechanical Data ±1 List of Illustrations List of Tables Introduction FeaturesTCM4300 Functional Block Diagram Fmrxen Pin AssignmentsPZ Package TOP View VSSTerminal Description Name Terminal FunctionsDvss DsprwDspstrbl DvddMcrw McdsMTS1 MclkinSyndta ScenSint SynclkDerating Factor Power Rating Above TA = 25CDissipation Rating Table PackagePower Consumption Reference CharacteristicsRecommended Operating Conditions Parameter Test Conditions MIN TYP MAX Unit Terminal ImpedanceRXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Function MIN TYP² MAX UnitTransmit I and Q Channel Outputs Auxiliary D/A ConvertersParameter MIN TYP MAX Unit Nominal LSB Nominal Output Voltage RSSI/Battery A/D ConverterAuxiliary D/A Converters Slope AGC, AFC, Pwrcont Auxiliary D/A Converters Slope LcdcontrTransmit TX Channel Frequency Response Digital Mode Transmit TX Channel Frequency Response Analog Mode Page Mclkout Timing Requirements see ±1 and Note MclkoutVOH VOL MCA4±MCA0 MCD7±MCD0 Mccsh Mccsl Parameter Alternate MIN MAX UnitMcds McrwMCA4±MCA0 Parameter Alternate MIN MAX Unit SymbolMCA4±MCA0 MCD7±MCD0 Twdho MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl Motorola 16-Bit Read Cycle, MTS 10 =MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl Mcrw MCA0±MCA410% ThR / W ThWA Dspa Dspd DspcslDspstrbl Dsprw±11. TCM4300 to DSP Interface Write Cycle ±12 Data Transfer ±1. TCM4300 Receive Channel Control SignalsControl Signal Analog Mode Digital Mode Mode Fmvox Iqrxen Fmrxen±2. RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Transmit Section ±5. Transmit TX I and Q Channel Outputs Modulation error percentage +100 s %Transmit Burst Operation Digital Mode ±6. Transmit TX Channel Frequency Response Digital Mode±7. Transmit TX Channel Frequency Response Analog Mode ±1. Power Ramp-Up/Ramp-Down TIming Diagram Wide-Band Data Demodulator Transmit I And Q Output LevelParameter Test Conditions MIN MAX Unit Mean CNR ±8. Typical Bit-Error-Rate Performance Wbdbw =Wide-band Data Interrupts ±9. Bits in Control Register WBDCtrlWBD Wide-band Data Demodulator General InformationAuxiliary DACs, LCD Contrast Converter ±10. Auxiliary D/A Converters±11. Auxiliary D /A Converters Slope AGC, AFC, Pwrcont ±12. Auxiliary D /A Converters Slope Lcdcontr RSSI, Battery Monitor±13. RSSI/Battery A/D Converter Timing And Clock GenerationSample Interrupt Sint Clock GenerationSpeech-Codec Clock Generation Microcontroller ClockPhase-Adjustment Strategy RCO MclkinMclken Frequency Synthesizer Interface Syndta Clkpol Numclks LowvalHighval MSB/LSB FirstName Description ±14. Synthesizer Control FieldsSynclk Syndta SYNLE1 SYNLE0 Synrdy Power Control Port15. External Power Control Signals Name Suggested External Application ResetFmrxen Scen Iqrxen Txen ModeWBD Wbdon OUT1Cint DSP Microcontroller-DSP CommunicationsDint Fifo a Fifo B±16. Microcontroller Register Map Microcontroller Register MapWide-Band Data/Control Register ±17. Microcontroller Register DefinitionsAddr Name Category BIT Name Function Reset Value Microcontroller Status and Control Registers±18. WBDCtrl Register Lcden LCD Contrast±19. MStatCtrl Register Bits LDC D/ADSP Register Map ±20. DSP Register Map±21. DSP Register Definitions DSP Strb INT Wide-Band Data RegistersBase Station Offset Register Dspcsl TCM4300 Dsprw Dspstrbl Sint Cint Bdint±22. DStatCtrl Register Bits DSP Status and Control Registers±23. Power-On Reset Register Initialization ResetPower-On Reset Internal Reset StateMicrocontroller Interface Intel Microcontroller Mode Of Operation±24. Microcontroller Interface Configuration ±25. Microcontroller Interface Connections for Intel ModeIRQ NMI Dint Mitsubishi Microcontroller Mode of OperationMotorola Microcontroller Mode of Operation Mcrw McdsCS3 ±32 PZ S-PQFP-G100 Mechanical DataImportant Notice