Texas Instruments TCM4300 Data Transfer, Receive Section, Control Signal Analog Mode Digital Mode

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4 Principles of Operation

This section describes the operation of the TCM4300 in detail.

NOTE:

Timing diagrams and associated tables are contained in Section 3 of this data manual.

4.1Data Transfer

The interface to both the system digital signal processor and microcontroller is in the form of 2s complement.

4.2Receive Section

The mode of operation is determined by the state of the MODE, FMVOX, IQRXEN, and FMRXEN bits of the DStatCtrl register, as shown in Table 4±1.

Table 4±1. TCM4300 Receive Channel Control Signals

CONTROL SIGNAL

ANALOG MODE

DIGITAL MODE

 

 

 

MODE

0

1

 

 

 

FMVOX

1

0

 

 

 

IQRXEN

0

1

 

 

 

FMRXEN

1

0

 

 

 

In the digital mode (MODE=1), the receive section accepts RXIP, RXIN, RXQP, and RXQN analog inputs. These inputs are passed to continuous-time antialiasing filters (AAF), baseband filtering, and A/D conversion blocks, and then to sample registers where 10-bit registers can be read. The sample rate is 48.6 ksps.

In the analog mode (MODE = 0), the FMVOX bit of the DStatCtrl register enables or disables the Q side of the receiver channel, and the FMRXEN bit controls the external functions. In the digital mode, IQRXEN enables both the I and Q receive channels and external functions as well.

To save power, the receive I and Q channels are enabled separately. This operation occurs because in the analog mode, only the Q channel is used. When the FMVOX bit is set to 1, it controls the input multiplexer, connects the FM input to the receiver RXQP signal, and connects the RXQN signal to VHR. When the MODE control bit and the IQRXEN control bit are set to 1, both sides of the receive channel are enabled for use in the digital mode.

The input signals RXIP, RXIN and RXQP, RXQN are differential pair signals (see Table 4±2). Differential signals are used to minimize the pickup of interference, ground, and supply noise, while maintaining a larger signal level. In single-ended applications, the unused RXIN and RXQN terminals must be connected to VHR or to an externally supplied bias voltage equal to the dc value of the input signal, and the input signal level must be adjusted in the RF circuitry to provide the proper signal level so that the digital output codes are properly calibrated (0.5 V peak-to-peak corresponds to full-scale digital output). In the analog mode, the RXQN input is internally referenced to VHR. Alternatively, the unused inputs can be connected to VHR and the used inputs can be capacitively coupled. Note that when the RX and FM inputs are capacitively coupled, it is recommended that the input terminals be connected to VHR using a bias resistor.

4±1

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Contents Data Manual SLWS010F TCM4300 Data Manual Important Notice Contents Mechanical Data ±1 List of Illustrations List of Tables Features IntroductionTCM4300 Functional Block Diagram Pin Assignments PZ Package TOP ViewVSS FmrxenTerminal Functions Terminal Description NameDsprw DspstrblDvdd DvssMcds MTS1Mclkin McrwScen SintSynclk SyndtaPower Rating Above TA = 25C Dissipation Rating TablePackage Derating FactorPower Consumption Reference CharacteristicsRecommended Operating Conditions Terminal Impedance RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5Function MIN TYP² MAX Unit Parameter Test Conditions MIN TYP MAX UnitTransmit I and Q Channel Outputs Auxiliary D/A ConvertersParameter MIN TYP MAX Unit RSSI/Battery A/D Converter Auxiliary D/A Converters Slope AGC, AFC, PwrcontAuxiliary D/A Converters Slope Lcdcontr Nominal LSB Nominal Output VoltageTransmit TX Channel Frequency Response Digital Mode Transmit TX Channel Frequency Response Analog Mode Page Mclkout Timing Requirements see ±1 and Note MclkoutVOH VOL Parameter Alternate MIN MAX Unit McdsMcrw MCA4±MCA0 MCD7±MCD0 Mccsh MccslParameter Alternate MIN MAX Unit Symbol MCA4±MCA0MCA4±MCA0 MCD7±MCD0 Twdho Motorola 16-Bit Read Cycle, MTS 10 = MCA0±MCA4 MCD0±MCD7 Mccsh MccslMCA0±MCA4 Mcrw MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl10% ThR / W ThWA Dspcsl DspstrblDsprw Dspa Dspd±11. TCM4300 to DSP Interface Write Cycle ±12 ±1. TCM4300 Receive Channel Control Signals Control Signal Analog Mode Digital ModeMode Fmvox Iqrxen Fmrxen Data Transfer±2. RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Transmit Section Modulation error percentage +100 s % ±5. Transmit TX I and Q Channel OutputsTransmit Burst Operation Digital Mode ±6. Transmit TX Channel Frequency Response Digital Mode±7. Transmit TX Channel Frequency Response Analog Mode ±1. Power Ramp-Up/Ramp-Down TIming Diagram Transmit I And Q Output Level Wide-Band Data Demodulator±8. Typical Bit-Error-Rate Performance Wbdbw = Wide-band Data Interrupts±9. Bits in Control Register WBDCtrl Parameter Test Conditions MIN MAX Unit Mean CNRWide-band Data Demodulator General Information WBDAuxiliary DACs, LCD Contrast Converter ±10. Auxiliary D/A Converters±11. Auxiliary D /A Converters Slope AGC, AFC, Pwrcont RSSI, Battery Monitor ±13. RSSI/Battery A/D ConverterTiming And Clock Generation ±12. Auxiliary D /A Converters Slope LcdcontrClock Generation Speech-Codec Clock GenerationMicrocontroller Clock Sample Interrupt SintPhase-Adjustment Strategy RCO MclkinMclken Frequency Synthesizer Interface Clkpol Numclks Lowval HighvalMSB/LSB First Syndta±14. Synthesizer Control Fields Name DescriptionPower Control Port 15. External Power Control SignalsName Suggested External Application Reset Synclk Syndta SYNLE1 SYNLE0 SynrdyIqrxen Txen Mode WBD WbdonOUT1 Fmrxen ScenMicrocontroller-DSP Communications DintFifo a Fifo B Cint DSPMicrocontroller Register Map ±16. Microcontroller Register MapWide-Band Data/Control Register ±17. Microcontroller Register DefinitionsAddr Name Category BIT Name Function Reset Value Microcontroller Status and Control Registers±18. WBDCtrl Register LCD Contrast ±19. MStatCtrl Register BitsLDC D/A LcdenDSP Register Map ±20. DSP Register Map±21. DSP Register Definitions Wide-Band Data Registers Base Station Offset RegisterDspcsl TCM4300 Dsprw Dspstrbl Sint Cint Bdint DSP Strb INTDSP Status and Control Registers ±22. DStatCtrl Register BitsReset Power-On ResetInternal Reset State ±23. Power-On Reset Register InitializationIntel Microcontroller Mode Of Operation ±24. Microcontroller Interface Configuration±25. Microcontroller Interface Connections for Intel Mode Microcontroller InterfaceMitsubishi Microcontroller Mode of Operation Motorola Microcontroller Mode of OperationMcrw Mcds IRQ NMI DintCS3 ±32 Mechanical Data PZ S-PQFP-G100Important Notice