Texas Instruments TCM4300 manual Power Control Port, External Power Control Signals

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Up to 31 data bits plus a latch enable (SYNLE0,1,2) can be programmed in one programming cycle. When data greater than or equal to 32 bits must be programmed, TI recommends using two or more programming cycles with data in each cycle and a latch enable in the final programming cycle. Two or more programming cycles are recommended because all programming cycles must contain at least one SYNCLK pulse, whereas the latch enable can be suppressed in any programming cycle.

Figure 4±8 shows an example of the synthesizer output signals. In this case, an 18-bit pattern, 0x10664, was chosen to write into synthesizer 1 with a positive-going latch enable pulse at the eighteenth bit. In order to do so, the microcontroller writes the values 00h into SynData0, 00h into SynData1, 99h into SynData2, 41h into SynData3, 52h into SynCtrl0, 31h into SynCtrl1, and 32h into SynCtrl2.

SYNCLK

SYNDTA

1

SYNLE1

SYNLE0, 2

SYNRDY

0

6

6

4

Figure 4±8. Example Synthesizer Output

4.13 Power Control Port

For systems requiring minimum system current consumption, power can be provided to each functional part of the TCM4300 only when that function is required for proper system operation. To accomplish this, the TCM4300 provides six external power control signals accessible through the DStatCtrl and MStatCtrl registers. These signals can be used to minimize the on time of the functional units. These power control signals are SCEN, FMRXEN, IQRXEN, TXEN, PAEN, and OUT1 (see Table 4±15). The polarity of each of these signals is high enable, low disable.

Table 4-15. External Power Control Signals

	NAME	SUGGESTED EXTERNAL APPLICATION	RESET
	NAME	SUGGESTED EXTERNAL APPLICATION	VALUE
			VALUE

	SCEN	Speech codec (microphone/speaker interface circuit) enable	0

	FMRXEN	FM demodulator enable	0

	IQRXEN	I and Q receive enable. IQRXEN enables the QPSK demodulator and the AGC amplifier	0

	TXEN	Transmit enable. TXEN enables power to the transmitter signal processing circuits: QPSK	0
		modulator, voltage-controlled amplifier, driver amplifier, PA negative bias. This signal can
		be used to enable these subsystems only during the transmit burst in digital mode.

	OUT1	User defined	0

	PAEN	Power amplifier enable. PAEN enables power to PA.	0

4±18

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Contents Data Manual SLWS010F TCM4300 Data Manual Important Notice Contents Mechanical Data ±1 List of Illustrations List of Tables Introduction FeaturesTCM4300 Functional Block Diagram PZ Package TOP View Pin AssignmentsVSS FmrxenTerminal Description Name Terminal FunctionsDspstrbl DsprwDvdd DvssMTS1 McdsMclkin McrwSint ScenSynclk SyndtaDissipation Rating Table Power Rating Above TA = 25CPackage Derating FactorRecommended Operating Conditions Power ConsumptionReference Characteristics RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Terminal ImpedanceFunction MIN TYP² MAX Unit Parameter Test Conditions MIN TYP MAX UnitParameter MIN TYP MAX Unit Transmit I and Q Channel OutputsAuxiliary D/A Converters Auxiliary D/A Converters Slope AGC, AFC, Pwrcont RSSI/Battery A/D ConverterAuxiliary D/A Converters Slope Lcdcontr Nominal LSB Nominal Output VoltageTransmit TX Channel Frequency Response Digital Mode Transmit TX Channel Frequency Response Analog Mode Page VOH VOL Mclkout Timing Requirements see ±1 and NoteMclkout Mcds Parameter Alternate MIN MAX UnitMcrw MCA4±MCA0 MCD7±MCD0 Mccsh MccslMCA4±MCA0 Parameter Alternate MIN MAX Unit SymbolMCA4±MCA0 MCD7±MCD0 Twdho MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl Motorola 16-Bit Read Cycle, MTS 10 =MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl Mcrw MCA0±MCA410% ThR / W ThWA Dspstrbl DspcslDsprw Dspa Dspd±11. TCM4300 to DSP Interface Write Cycle ±12 Control Signal Analog Mode Digital Mode ±1. TCM4300 Receive Channel Control SignalsMode Fmvox Iqrxen Fmrxen Data Transfer±2. RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Transmit Section ±5. Transmit TX I and Q Channel Outputs Modulation error percentage +100 s %±7. Transmit TX Channel Frequency Response Analog Mode Transmit Burst Operation Digital Mode±6. Transmit TX Channel Frequency Response Digital Mode ±1. Power Ramp-Up/Ramp-Down TIming Diagram Wide-Band Data Demodulator Transmit I And Q Output LevelWide-band Data Interrupts ±8. Typical Bit-Error-Rate Performance Wbdbw =±9. Bits in Control Register WBDCtrl Parameter Test Conditions MIN MAX Unit Mean CNRWBD Wide-band Data Demodulator General Information±11. Auxiliary D /A Converters Slope AGC, AFC, Pwrcont Auxiliary DACs, LCD Contrast Converter±10. Auxiliary D/A Converters ±13. RSSI/Battery A/D Converter RSSI, Battery MonitorTiming And Clock Generation ±12. Auxiliary D /A Converters Slope LcdcontrSpeech-Codec Clock Generation Clock GenerationMicrocontroller Clock Sample Interrupt SintPhase-Adjustment Strategy Mclken RCOMclkin Frequency Synthesizer Interface Highval Clkpol Numclks LowvalMSB/LSB First SyndtaName Description ±14. Synthesizer Control Fields15. External Power Control Signals Power Control PortName Suggested External Application Reset Synclk Syndta SYNLE1 SYNLE0 SynrdyWBD Wbdon Iqrxen Txen ModeOUT1 Fmrxen ScenDint Microcontroller-DSP CommunicationsFifo a Fifo B Cint DSP±16. Microcontroller Register Map Microcontroller Register MapAddr Name Category Wide-Band Data/Control Register±17. Microcontroller Register Definitions ±18. WBDCtrl Register BIT Name Function Reset ValueMicrocontroller Status and Control Registers ±19. MStatCtrl Register Bits LCD ContrastLDC D/A Lcden±21. DSP Register Definitions DSP Register Map±20. DSP Register Map Base Station Offset Register Wide-Band Data RegistersDspcsl TCM4300 Dsprw Dspstrbl Sint Cint Bdint DSP Strb INT±22. DStatCtrl Register Bits DSP Status and Control RegistersPower-On Reset ResetInternal Reset State ±23. Power-On Reset Register Initialization±24. Microcontroller Interface Configuration Intel Microcontroller Mode Of Operation±25. Microcontroller Interface Connections for Intel Mode Microcontroller InterfaceMotorola Microcontroller Mode of Operation Mitsubishi Microcontroller Mode of OperationMcrw Mcds IRQ NMI DintCS3 ±32 PZ S-PQFP-G100 Mechanical DataImportant Notice