Texas Instruments TCM4300 Auxiliary DACs, LCD Contrast Converter, ±10. Auxiliary D/A Converters

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4.9Auxiliary DACs, LCD Contrast Converter

Auxiliary DACs generate AFC, AGC and power control signals for the RF system. These three D/A converters are updated when the corresponding data is received from the DSP. In fewer than 5 μs after the corresponding registers are written to, the output has settled to within 1 LSB of its new value (see Table 4±10).

Table 4±10. Auxiliary D/A Converters

PARAMETER

TEST CONDITIONS

MIN TYP

MAX

UNIT

 

 

 

 

 

 

 

AVDD > 3 V² ,

AUXFS [1:0] = 00

0.2

2.5

 

Output range

AVDD > 4.5 V² ,

AUXFS [1:0] = 10

0.2

4

V

 

AVDD > 5 V² ,

AUXFS [1:0] = 11

0.2

4.5

 

Resolution AGC, AFC, PWRCONT

 

 

8

 

bits

DACs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Resolution LCDCONTR DAC

 

 

4

 

bits

 

 

 

 

 

 

Gain + offset error (full scale) AGC,

 

 

 

± 3%

 

AFC, PWRCONT DAC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Gain + offset error (full scale)

 

 

 

± 7%

 

LCDCONTR DAC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Differential nonlinearity

 

 

± 0.75

± 1

LSB

 

 

 

 

 

 

Integral nonlinearity

 

 

± 0.75

± 1

LSB

² Range settings depends only on AUXFS [1:0]. The supply voltage is not detected.

The LCDCONTR output is used by the microcontroller to adjust the contrast of the liquid-crystal display (LCD). This converter is a separate 4-bit DAC.

The auxiliary DACs can be powered down. The AGC and AFC DACs have dedicated bits in the MIntCtrl register to enable the DACs. The PWRCONT DAC is enabled by the TXEN bit in the DStatCtrl register. The LCDCONTR DAC is enabled when the LCDEN bit of the LCD D/A register clears to 0, the four data bits being left justified. The AFC, AGC, and PWRCONT DACs are disabled after powerup or after a reset of the TCM4300. After power up or reset, the default AUXFS[1:0] is 00. When the DACs are powered down, their output terminals go to a high-impedance state and can tolerate any voltage present on the terminal that falls within the supply range.

The slope and the corresponding output values for the auxiliary DACs are listed in Table 4±11 and Table 4±12.

Table 4±11. Auxiliary D /A Converters Slope (AGC, AFC, PWRCONT)

 

 

NOMINAL LSB

NOMINAL OUTPUT VOLTAGE

NOMINAL OUTPUT VOLTAGE

AUXFS[1:0]

 

FOR DIGITAL CODE = 128

FOR DIGITAL CODE = 256³

SLOPE

VALUE

SETTING

(MIDRANGE)

(MAX VALUE)

 

(V)

 

 

(V)

(V)

 

 

 

 

 

 

 

 

00

2.5/256

0.0098

1.25

2.5

 

 

 

 

 

01

Do not use

Do not use

Do not use

Do not use

 

 

 

 

 

10

4/256

0.0156

2

4

 

 

 

 

 

11

4.5/256

0.0176

2.25

4.5

 

 

 

 

 

³ The maximum input code is 255. The value shown for 256 is extrapolated.

4±10

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Contents Data Manual SLWS010F TCM4300 Data Manual Important Notice Contents Mechanical Data ±1 List of Illustrations List of Tables Introduction FeaturesTCM4300 Functional Block Diagram PZ Package TOP View Pin AssignmentsVSS FmrxenTerminal Description Name Terminal FunctionsDspstrbl DsprwDvdd DvssMTS1 McdsMclkin McrwSint ScenSynclk SyndtaDissipation Rating Table Power Rating Above TA = 25CPackage Derating FactorPower Consumption Reference CharacteristicsRecommended Operating Conditions RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Terminal ImpedanceFunction MIN TYP² MAX Unit Parameter Test Conditions MIN TYP MAX UnitTransmit I and Q Channel Outputs Auxiliary D/A ConvertersParameter MIN TYP MAX Unit Auxiliary D/A Converters Slope AGC, AFC, Pwrcont RSSI/Battery A/D ConverterAuxiliary D/A Converters Slope Lcdcontr Nominal LSB Nominal Output VoltageTransmit TX Channel Frequency Response Digital Mode Transmit TX Channel Frequency Response Analog Mode Page Mclkout Timing Requirements see ±1 and Note MclkoutVOH VOL Mcds Parameter Alternate MIN MAX UnitMcrw MCA4±MCA0 MCD7±MCD0 Mccsh MccslMCA4±MCA0 Parameter Alternate MIN MAX Unit SymbolMCA4±MCA0 MCD7±MCD0 Twdho MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl Motorola 16-Bit Read Cycle, MTS 10 =MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl Mcrw MCA0±MCA410% ThR / W ThWA Dspstrbl DspcslDsprw Dspa Dspd±11. TCM4300 to DSP Interface Write Cycle ±12 Control Signal Analog Mode Digital Mode ±1. TCM4300 Receive Channel Control SignalsMode Fmvox Iqrxen Fmrxen Data Transfer±2. RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Transmit Section ±5. Transmit TX I and Q Channel Outputs Modulation error percentage +100 s %Transmit Burst Operation Digital Mode ±6. Transmit TX Channel Frequency Response Digital Mode±7. Transmit TX Channel Frequency Response Analog Mode ±1. Power Ramp-Up/Ramp-Down TIming Diagram Wide-Band Data Demodulator Transmit I And Q Output LevelWide-band Data Interrupts ±8. Typical Bit-Error-Rate Performance Wbdbw =±9. Bits in Control Register WBDCtrl Parameter Test Conditions MIN MAX Unit Mean CNRWBD Wide-band Data Demodulator General InformationAuxiliary DACs, LCD Contrast Converter ±10. Auxiliary D/A Converters±11. Auxiliary D /A Converters Slope AGC, AFC, Pwrcont ±13. RSSI/Battery A/D Converter RSSI, Battery MonitorTiming And Clock Generation ±12. Auxiliary D /A Converters Slope LcdcontrSpeech-Codec Clock Generation Clock GenerationMicrocontroller Clock Sample Interrupt SintPhase-Adjustment Strategy RCO MclkinMclken Frequency Synthesizer Interface Highval Clkpol Numclks LowvalMSB/LSB First SyndtaName Description ±14. Synthesizer Control Fields15. External Power Control Signals Power Control PortName Suggested External Application Reset Synclk Syndta SYNLE1 SYNLE0 SynrdyWBD Wbdon Iqrxen Txen ModeOUT1 Fmrxen ScenDint Microcontroller-DSP CommunicationsFifo a Fifo B Cint DSP±16. Microcontroller Register Map Microcontroller Register MapWide-Band Data/Control Register ±17. Microcontroller Register DefinitionsAddr Name Category BIT Name Function Reset Value Microcontroller Status and Control Registers±18. WBDCtrl Register ±19. MStatCtrl Register Bits LCD ContrastLDC D/A LcdenDSP Register Map ±20. DSP Register Map±21. DSP Register Definitions Base Station Offset Register Wide-Band Data RegistersDspcsl TCM4300 Dsprw Dspstrbl Sint Cint Bdint DSP Strb INT±22. DStatCtrl Register Bits DSP Status and Control RegistersPower-On Reset ResetInternal Reset State ±23. Power-On Reset Register Initialization±24. Microcontroller Interface Configuration Intel Microcontroller Mode Of Operation±25. Microcontroller Interface Connections for Intel Mode Microcontroller InterfaceMotorola Microcontroller Mode of Operation Mitsubishi Microcontroller Mode of OperationMcrw Mcds IRQ NMI DintCS3 ±32 PZ S-PQFP-G100 Mechanical DataImportant Notice