Texas Instruments TCM4300 manual LCD Contrast, ±19. MStatCtrl Register Bits, Ldc D/A, Lcden

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Table 4±19. MStatCtrl Register Bits

BIT

R / W

NAME

FUNCTION

RESET VALUE

 

 

 

 

 

 

 

 

Synthesizer out of lock. SYNOL is equal to the level applied to SYNOL

 

 

 

 

input pin. SYNOL can be used as an input for an externally generated

Level on

7

R

SYNOL

status signal to prevent transmission when external synthesizers are

SYNOL input

 

 

 

out of lock. In digital mode, when SYNOL is high, PAEN is not asserted

terminals

 

 

 

and no signal can be transmitted from TXIP, TXIN, TXQP, and TXQN.

 

 

 

 

 

 

 

 

 

Transmitter on indicator. TXONIND is equal to the level applied to

Level for

6

R

TXONIND

TXONIND, and it can indicate that power is applied to the power

TXONIND input

 

 

 

amplifier.

terminals

 

 

 

 

 

 

 

 

Synthesizer interface ready. SYNRDY indicates that frequency

 

5

R

SYNRDY

synthesizer is ready to be programmed by the microcontroller. When

1

SYNRDY is 1, the microcontroller can program the frequency

 

 

 

 

 

 

 

synthesizer interface; a 0 indicates the interface circuit is busy.

 

 

 

 

 

 

 

 

 

MCLKOUT enable. When MCLKEN is set to 1 by the microcontroller,

 

4

R / W

MCLKEN

the 38.88-MHz master clock is output at MCLKOUT. Writing 0 to

1

 

 

 

MCLKEN disables MCLKOUT.

 

 

 

 

 

 

 

 

 

Conversion ready. A 1 indicates that the latest RSSI or battery voltage

 

3

R

CVRDY

A/D conversion is complete and can be read from the RSSI or battery

1

register location. CVRDY goes to 0 when the microcontroller reads from

 

 

 

 

 

 

 

either of these locations.

 

 

 

 

 

 

2

 

AuxFS[1]

Auxiliary DACs full-scale select. The auxiliary DACs are AGC, AFC,

0

 

PWRCONT and also LCD CONTR DAC. The microcontroller selects

 

R / W

 

 

1

AuxFS[0]

the full-scale output ranges with these bits (see Table 4±11 and

0

 

 

Table 4±12 for bit-to-output range mapping).

 

 

 

 

 

 

 

 

 

0

R / W

MPAEN

Microcontroller PA enable. A 0 indicates that the external PA enable line

0

PAEN is prevented from going active (see Figure 4±9).

 

 

 

 

 

 

 

 

 

TXI Offset and TXQ Offset: These registers allow the differential offset voltages TXIP ± TXIN and TXQP ± TXQN to be adjusted to compensate for internal and/or external offsets. The magnitude of adjustment is D step size, where D is a 6-bit, 2s-complement integer written into bits 5±0 of these registers, as shown here:

 

7 ± 6

5 ± 0

TXI(Q) Offset

 

 

Reserved

TXI(Q) Offset Value

 

 

 

 

 

W

4.18 LCD Contrast

The LCD contrast register allows for 16 levels of control of terminal LCD contrast. The register is input to the LCD contrast D/A converter allowing control of the level of intensity of the LCD display as shown here:

 

7 ± 4

3 ± 1

0

 

 

 

 

LDC D/A

LCD Contrast

Reserved

LCDEN

(active low)

 

 

 

 

 

 

 

 

W

 

W

4±24

Image 59
Contents Data Manual SLWS010F TCM4300 Data Manual Important Notice Contents Mechanical Data ±1 List of Illustrations List of Tables Introduction FeaturesTCM4300 Functional Block Diagram Fmrxen Pin AssignmentsPZ Package TOP View VSSTerminal Description Name Terminal FunctionsDvss DsprwDspstrbl DvddMcrw McdsMTS1 MclkinSyndta ScenSint SynclkDerating Factor Power Rating Above TA = 25CDissipation Rating Table PackageRecommended Operating Conditions Power ConsumptionReference Characteristics Parameter Test Conditions MIN TYP MAX Unit Terminal ImpedanceRXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Function MIN TYP² MAX UnitParameter MIN TYP MAX Unit Transmit I and Q Channel OutputsAuxiliary D/A Converters Nominal LSB Nominal Output Voltage RSSI/Battery A/D ConverterAuxiliary D/A Converters Slope AGC, AFC, Pwrcont Auxiliary D/A Converters Slope LcdcontrTransmit TX Channel Frequency Response Digital Mode Transmit TX Channel Frequency Response Analog Mode Page VOH VOL Mclkout Timing Requirements see ±1 and NoteMclkout MCA4±MCA0 MCD7±MCD0 Mccsh Mccsl Parameter Alternate MIN MAX UnitMcds McrwMCA4±MCA0 Parameter Alternate MIN MAX Unit SymbolMCA4±MCA0 MCD7±MCD0 Twdho MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl Motorola 16-Bit Read Cycle, MTS 10 =MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl Mcrw MCA0±MCA410% ThR / W ThWA Dspa Dspd DspcslDspstrbl Dsprw±11. TCM4300 to DSP Interface Write Cycle ±12 Data Transfer ±1. TCM4300 Receive Channel Control SignalsControl Signal Analog Mode Digital Mode Mode Fmvox Iqrxen Fmrxen±2. RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Transmit Section ±5. Transmit TX I and Q Channel Outputs Modulation error percentage +100 s %±7. Transmit TX Channel Frequency Response Analog Mode Transmit Burst Operation Digital Mode±6. Transmit TX Channel Frequency Response Digital Mode ±1. Power Ramp-Up/Ramp-Down TIming Diagram Wide-Band Data Demodulator Transmit I And Q Output LevelParameter Test Conditions MIN MAX Unit Mean CNR ±8. Typical Bit-Error-Rate Performance Wbdbw =Wide-band Data Interrupts ±9. Bits in Control Register WBDCtrlWBD Wide-band Data Demodulator General Information±11. Auxiliary D /A Converters Slope AGC, AFC, Pwrcont Auxiliary DACs, LCD Contrast Converter±10. Auxiliary D/A Converters ±12. Auxiliary D /A Converters Slope Lcdcontr RSSI, Battery Monitor±13. RSSI/Battery A/D Converter Timing And Clock GenerationSample Interrupt Sint Clock GenerationSpeech-Codec Clock Generation Microcontroller ClockPhase-Adjustment Strategy Mclken RCOMclkin Frequency Synthesizer Interface Syndta Clkpol Numclks LowvalHighval MSB/LSB FirstName Description ±14. Synthesizer Control FieldsSynclk Syndta SYNLE1 SYNLE0 Synrdy Power Control Port15. External Power Control Signals Name Suggested External Application ResetFmrxen Scen Iqrxen Txen ModeWBD Wbdon OUT1Cint DSP Microcontroller-DSP CommunicationsDint Fifo a Fifo B±16. Microcontroller Register Map Microcontroller Register MapAddr Name Category Wide-Band Data/Control Register±17. Microcontroller Register Definitions ±18. WBDCtrl Register BIT Name Function Reset ValueMicrocontroller Status and Control Registers Lcden LCD Contrast±19. MStatCtrl Register Bits LDC D/A±21. DSP Register Definitions DSP Register Map±20. DSP Register Map DSP Strb INT Wide-Band Data RegistersBase Station Offset Register Dspcsl TCM4300 Dsprw Dspstrbl Sint Cint Bdint±22. DStatCtrl Register Bits DSP Status and Control Registers±23. Power-On Reset Register Initialization ResetPower-On Reset Internal Reset StateMicrocontroller Interface Intel Microcontroller Mode Of Operation±24. Microcontroller Interface Configuration ±25. Microcontroller Interface Connections for Intel ModeIRQ NMI Dint Mitsubishi Microcontroller Mode of OperationMotorola Microcontroller Mode of Operation Mcrw McdsCS3 ±32 PZ S-PQFP-G100 Mechanical DataImportant Notice