Texas Instruments TCM4300 manual Microcontroller-DSP Communications, Dint, Fifo a Fifo B, Cint DSP

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In the analog mode, (MODE bit set low), PAEN is high whenever TXEN is active and SYNOL is low. The SYNOL input can be used as an indication to the TCM4300 that the external synthesizers are out of lock. The PAEN signal is gated by SYNOL to prevent off-channel transmissions.

The TXEN, IQRXEN, FMVOX, and MODE signals are generated by sampling the corresponding bits of the DStatCtrl register with the internal SINT. The effect of a write to the DStatCtrl register on these signals does not appear until the next SINT after the write.

4.14 Microcontroller-DSP Communications

The microcontroller and the DSP communicate by means of two separate 32-byte first-in first-out (FIFO) buffers. Figure 4±10 illustrates this scheme. The microcontroller writes to FIFO A, but data read from the same address comes from FIFO B. On the DSP side, the situation is reversed.

8

μC

DINT

Send CINT,

CINT Status,

Clear DINT

FIFO A

8

FIFO B

Send DINT,

DINT Status,

Clear CINT

CINT

DSP

Figure 4±10. Microcontroller-DSP Data Buffers

To send data to the DSP, the microcontroller writes data to FIFO A. To indicate to the DSP that FIFO A is ready to be read, the microcontroller writes a 1 to the Send-C bit of the microcontroller interrupt control register MIntCtrl. When this happens, the DSP interrupt line CINT goes active, signaling to the DSP that data is waiting. At the same time, the value that can be read from the Clear-C bit in the DIntCtrl register goes from 0 to 1, indicating that the interrupt is pending. When the DSP writes a 1 to the Clear-C bit, the CINT line returns to the inactive state and the value that can be read from Clear-C is 0. The microcontroller cannot deassert the CINT line.

The microcontroller-DSP communications interface is symmetric. Data sent from the DSP to the microcontroller is handled as described above, with the roles of A and B FIFOs and C and D bits and interrupts reversed. When the number of reads exceeds the number of writes from the other side, the values read are undefined.

4±20

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Contents Data Manual SLWS010F TCM4300 Data Manual Important Notice Contents Mechanical Data ±1 List of Illustrations List of Tables Introduction FeaturesTCM4300 Functional Block Diagram Fmrxen Pin AssignmentsPZ Package TOP View VSSTerminal Description Name Terminal FunctionsDvss DsprwDspstrbl DvddMcrw McdsMTS1 MclkinSyndta ScenSint SynclkDerating Factor Power Rating Above TA = 25CDissipation Rating Table PackageReference Characteristics Power ConsumptionRecommended Operating Conditions Parameter Test Conditions MIN TYP MAX Unit Terminal ImpedanceRXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Function MIN TYP² MAX UnitAuxiliary D/A Converters Transmit I and Q Channel OutputsParameter MIN TYP MAX Unit Nominal LSB Nominal Output Voltage RSSI/Battery A/D ConverterAuxiliary D/A Converters Slope AGC, AFC, Pwrcont Auxiliary D/A Converters Slope LcdcontrTransmit TX Channel Frequency Response Digital Mode Transmit TX Channel Frequency Response Analog Mode Page Mclkout Mclkout Timing Requirements see ±1 and NoteVOH VOL MCA4±MCA0 MCD7±MCD0 Mccsh Mccsl Parameter Alternate MIN MAX UnitMcds McrwMCA4±MCA0 Parameter Alternate MIN MAX Unit SymbolMCA4±MCA0 MCD7±MCD0 Twdho MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl Motorola 16-Bit Read Cycle, MTS 10 =MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl Mcrw MCA0±MCA410% ThR / W ThWA Dspa Dspd DspcslDspstrbl Dsprw±11. TCM4300 to DSP Interface Write Cycle ±12 Data Transfer ±1. TCM4300 Receive Channel Control SignalsControl Signal Analog Mode Digital Mode Mode Fmvox Iqrxen Fmrxen±2. RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Transmit Section ±5. Transmit TX I and Q Channel Outputs Modulation error percentage +100 s %±6. Transmit TX Channel Frequency Response Digital Mode Transmit Burst Operation Digital Mode±7. Transmit TX Channel Frequency Response Analog Mode ±1. Power Ramp-Up/Ramp-Down TIming Diagram Wide-Band Data Demodulator Transmit I And Q Output LevelParameter Test Conditions MIN MAX Unit Mean CNR ±8. Typical Bit-Error-Rate Performance Wbdbw =Wide-band Data Interrupts ±9. Bits in Control Register WBDCtrlWBD Wide-band Data Demodulator General Information±10. Auxiliary D/A Converters Auxiliary DACs, LCD Contrast Converter±11. Auxiliary D /A Converters Slope AGC, AFC, Pwrcont ±12. Auxiliary D /A Converters Slope Lcdcontr RSSI, Battery Monitor±13. RSSI/Battery A/D Converter Timing And Clock GenerationSample Interrupt Sint Clock GenerationSpeech-Codec Clock Generation Microcontroller ClockPhase-Adjustment Strategy Mclkin RCOMclken Frequency Synthesizer Interface Syndta Clkpol Numclks LowvalHighval MSB/LSB FirstName Description ±14. Synthesizer Control FieldsSynclk Syndta SYNLE1 SYNLE0 Synrdy Power Control Port15. External Power Control Signals Name Suggested External Application ResetFmrxen Scen Iqrxen Txen ModeWBD Wbdon OUT1Cint DSP Microcontroller-DSP CommunicationsDint Fifo a Fifo B±16. Microcontroller Register Map Microcontroller Register Map±17. Microcontroller Register Definitions Wide-Band Data/Control RegisterAddr Name Category Microcontroller Status and Control Registers BIT Name Function Reset Value±18. WBDCtrl Register Lcden LCD Contrast±19. MStatCtrl Register Bits LDC D/A±20. DSP Register Map DSP Register Map±21. DSP Register Definitions DSP Strb INT Wide-Band Data RegistersBase Station Offset Register Dspcsl TCM4300 Dsprw Dspstrbl Sint Cint Bdint±22. DStatCtrl Register Bits DSP Status and Control Registers±23. Power-On Reset Register Initialization ResetPower-On Reset Internal Reset StateMicrocontroller Interface Intel Microcontroller Mode Of Operation±24. Microcontroller Interface Configuration ±25. Microcontroller Interface Connections for Intel ModeIRQ NMI Dint Mitsubishi Microcontroller Mode of OperationMotorola Microcontroller Mode of Operation Mcrw McdsCS3 ±32 PZ S-PQFP-G100 Mechanical DataImportant Notice