Texas Instruments TCM4300 manual Parameter Alternate MIN MAX Unit Symbol, MCA4±MCA0

Page 26

3.3TCM4300 to Microcontroller Interface Timing Requirements (Mitsubishi Write Cycle) (see Figure 3±3 and Note 2)

 

PARAMETER

ALTERNATE

MIN MAX

UNIT

 

SYMBOL

 

 

 

 

 

 

 

 

 

tsu(R/W)

Setup time, read/write MCRW stable before falling edge of

TRW(SU)

0

ns

strobe MCDS

 

 

 

 

 

 

 

 

 

th(R/W)

Hold time, read/write MCRW stable after rising edge of

TRW(HO)

10

ns

strobe MCDS

 

 

 

 

 

 

 

 

 

tsu(WA)

Setup time, write/address MCA stable before falling edge

TWA(SU)

0

ns

of strobe MCDS

 

 

 

 

 

 

 

 

 

th(WA)

Hold time, write address MCA stable after rising edge of

TWA(HO)

10

ns

strobe MCDS

 

 

 

 

 

 

 

 

 

tsu(W)

Setup time, write data stable MCD before rising edge of

TWD(SU)

14

ns

strobe MCDS

 

 

 

 

 

 

 

 

 

th(W)

Hold time, write data stable MCD after rising edge of strobe

TWD(HO)

0

ns

MCDS

 

 

 

 

 

 

 

 

 

tw(WSTB) Pulse duration, write strobe pulse width low on MCDS

TWR(STB)

60

ns

th(CS)

Hold time, chip select MCCSH and MCCSL stable before

TCS(HO)

0

ns

rising edge of strobe MCDS

 

 

 

 

 

 

 

 

 

tsu(CS)

Setup time, chip select stable MCCSH and MCCSL before

TCS(SU)

0

ns

falling edge of strobe MCDS

 

 

 

 

 

 

 

 

 

NOTE 2: Timings based upon Mitsubishi 37732S4 (16 MHz) and Mitsubishi 3772S4L (8 MHz).

 

 

tw(WSTB)

 

 

 

MCDS

90%

 

 

 

 

 

 

10%

10%

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(see Note A)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tsu(R / W)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MCRW

10%

tsu(WA)

MCA4±MCA0

90%

th(R / W)

10%

tsu(WA)

tsu(W)

MCD7±MCD0

90%

MCCSH

tsu(CS)

th(CS)

th(W)

90%

MCCSL

 

 

 

10%

10%

 

 

 

 

 

 

 

 

 

NOTE A: Chip selection is defined as both MCCS and MCDS active.

Figure 3±3. Microcontroller Interface Timing Requirements

(Mitsubishi Configuration Write Cycle, MTS [1:0] = 10)

3±3

Image 26
Contents Data Manual SLWS010F TCM4300 Data Manual Important Notice Contents Mechanical Data ±1 List of Illustrations List of Tables Features IntroductionTCM4300 Functional Block Diagram VSS Pin AssignmentsPZ Package TOP View FmrxenTerminal Functions Terminal Description NameDvdd DsprwDspstrbl DvssMclkin McdsMTS1 McrwSynclk ScenSint SyndtaPackage Power Rating Above TA = 25CDissipation Rating Table Derating FactorRecommended Operating Conditions Power ConsumptionReference Characteristics Function MIN TYP² MAX Unit Terminal ImpedanceRXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Parameter Test Conditions MIN TYP MAX UnitParameter MIN TYP MAX Unit Transmit I and Q Channel OutputsAuxiliary D/A Converters Auxiliary D/A Converters Slope Lcdcontr RSSI/Battery A/D ConverterAuxiliary D/A Converters Slope AGC, AFC, Pwrcont Nominal LSB Nominal Output VoltageTransmit TX Channel Frequency Response Digital Mode Transmit TX Channel Frequency Response Analog Mode Page VOH VOL Mclkout Timing Requirements see ±1 and NoteMclkout Mcrw Parameter Alternate MIN MAX UnitMcds MCA4±MCA0 MCD7±MCD0 Mccsh MccslParameter Alternate MIN MAX Unit Symbol MCA4±MCA0MCA4±MCA0 MCD7±MCD0 Twdho Motorola 16-Bit Read Cycle, MTS 10 = MCA0±MCA4 MCD0±MCD7 Mccsh MccslMCA0±MCA4 Mcrw MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl10% ThR / W ThWA Dsprw DspcslDspstrbl Dspa Dspd±11. TCM4300 to DSP Interface Write Cycle ±12 Mode Fmvox Iqrxen Fmrxen ±1. TCM4300 Receive Channel Control SignalsControl Signal Analog Mode Digital Mode Data Transfer±2. RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Transmit Section Modulation error percentage +100 s % ±5. Transmit TX I and Q Channel Outputs±7. Transmit TX Channel Frequency Response Analog Mode Transmit Burst Operation Digital Mode±6. Transmit TX Channel Frequency Response Digital Mode ±1. Power Ramp-Up/Ramp-Down TIming Diagram Transmit I And Q Output Level Wide-Band Data Demodulator±9. Bits in Control Register WBDCtrl ±8. Typical Bit-Error-Rate Performance Wbdbw =Wide-band Data Interrupts Parameter Test Conditions MIN MAX Unit Mean CNRWide-band Data Demodulator General Information WBD±11. Auxiliary D /A Converters Slope AGC, AFC, Pwrcont Auxiliary DACs, LCD Contrast Converter±10. Auxiliary D/A Converters Timing And Clock Generation RSSI, Battery Monitor±13. RSSI/Battery A/D Converter ±12. Auxiliary D /A Converters Slope LcdcontrMicrocontroller Clock Clock GenerationSpeech-Codec Clock Generation Sample Interrupt SintPhase-Adjustment Strategy Mclken RCOMclkin Frequency Synthesizer Interface MSB/LSB First Clkpol Numclks LowvalHighval Syndta±14. Synthesizer Control Fields Name DescriptionName Suggested External Application Reset Power Control Port15. External Power Control Signals Synclk Syndta SYNLE1 SYNLE0 SynrdyOUT1 Iqrxen Txen ModeWBD Wbdon Fmrxen ScenFifo a Fifo B Microcontroller-DSP CommunicationsDint Cint DSPMicrocontroller Register Map ±16. Microcontroller Register MapAddr Name Category Wide-Band Data/Control Register±17. Microcontroller Register Definitions ±18. WBDCtrl Register BIT Name Function Reset ValueMicrocontroller Status and Control Registers LDC D/A LCD Contrast±19. MStatCtrl Register Bits Lcden±21. DSP Register Definitions DSP Register Map±20. DSP Register Map Dspcsl TCM4300 Dsprw Dspstrbl Sint Cint Bdint Wide-Band Data RegistersBase Station Offset Register DSP Strb INTDSP Status and Control Registers ±22. DStatCtrl Register BitsInternal Reset State ResetPower-On Reset ±23. Power-On Reset Register Initialization±25. Microcontroller Interface Connections for Intel Mode Intel Microcontroller Mode Of Operation±24. Microcontroller Interface Configuration Microcontroller InterfaceMcrw Mcds Mitsubishi Microcontroller Mode of OperationMotorola Microcontroller Mode of Operation IRQ NMI DintCS3 ±32 Mechanical Data PZ S-PQFP-G100Important Notice