Texas Instruments TCM4300 Motorola 16-Bit Read Cycle, MTS 10 =, MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl

3.6TCM4300 to Microcontroller Interface Timing Requirements (Motorola 16-Bit Read Cycle) (see Figure 3±6 and Note 4)

	PARAMETER	ALTERNATE	MIN	MAX	UNIT
		SYMBOL
tsu(R/W)	Setup time, read/write MCRW stable before falling edge of	TRW(SU)	0		ns
	strobe MCDS
th(R/W)	Hold time, read/write MCRW stable after rising edge of	TRW(HO)	10		ns
	strobe MCDS
tsu(RA)	Setup time, read address MCA stable before falling edge of	TRA(SU)	0		ns
	strobe MCDS
th(RA)	Hold time, read address MCA stable after rising edge of	TRA(HO)	10		ns
	strobe MCDS
ten(RD)	Enable time, read data on falling edge of strobe MCDS to	TRD(EN)	10		ns
	TCM4300 driving data bus MCD
tv(RD)	Valid time, read data on falling edge of strobe MCDS to	TRD(DV)		50	ns
	valid data MCD
tinv	Data (MCD) invalid after rising edge of strobe MCDS	TRD(INV)		10	ns
tdis(RD)	Disable time, read data. TCM4300 releases MCD data bus	TRD(DIS)		28	ns
	after rising edge of strobe MCDS
th(CS)	Hold time, chip select MCCSH and MCCSL stable before	TCS(HO)	0		ns
	falling edge of strobe MCDS
tsu(CS)	Setup time, chip select stable MCCSH and MCCSL before	TCS(SU)	0		ns
	rising edge of strobe MCDS
NOTE 4: Timings are based upon Motorola 68HC000 (16.67 MHz) and Motorola 68302 (16 MHz).

MCDS	90%		90%
		10%	10%
(see Note A)

MCRW

tsu(R / W) 90%

tsu(RA)

th(R / W)

90%

th(RA)

MCA0±MCA4

MCD0±MCD7

MCCSH

MCCSL

tv(RD)	tdis(RD)
ten(RD)	tinv
90%	90%
tsu(CS)	th(CS)
10%	10%

NOTE A: Chip selection is defined as both MCCS and MCDS active.

Figure 3±6. Microcontroller Interface Timing Requirements

(Motorola 16-Bit Read Cycle, MTS [1:0] = 10)

3±6