Texas Instruments TCM4300 manual ±1. Power Ramp-Up/Ramp-Down TIming Diagram

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delay after the last symbol occurs (2 SINT periods before TXGO goes low); then the transmit outputs decay to zero differential voltage (each output at the voltage supplied to the VCM input terminal). The shape of the decay is the transient resulting from the internal SQRC filtering. The transmit outputs are held at zero differential voltage 6 SINT periods (3 symbol periods) after the start of the decay. At this time the PAEN digital output is set low (see Figure 4±1 and Figure 4±2).

Nonzero values of the BST offset register increase the delays of both the transmit waveforms and PAEN relative to the edges of TXGO after it is internally sampled by SINT. The delays are increased in increments of 1/4 SINT (1/8 symbol period).

For delays of 1 SINT or greater, the fractional part of the delay can be achieved using the BST offset register with the remaining integer SINT delay implemented externally by delaying the writing to TXGO and TXI.

The relative timing of PAEN and the transmit waveforms is not affected by the BST offset register.

The IS-54 standard describes shortened bursts and normal bursts. The two types differ in duration and number of transmitted bursts, burst length being determined by the TXGO bit.

N+3 SINT Periods

(N = Total number of bits sent)

19.5 SINT Periods +d(T/8)

6 SINT Periods

SINT

TXGO

TXI data bit

PAEN TXI/Q output ramp Input Bits Dibit transmission

9.5SINT Periods d(T/8)²

15.5 SINT Periods +d(T/8)

>>>

>>>

>>>

>>>

First MEP

Last MEP

²Total delay = d (SINT/4 or T/8) where d = integer value (0,1,2,3) written to the BST offset register.

Figure 4±1. Power Ramp-Up/Ramp-Down TIming Diagram

4±6

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Contents Data Manual SLWS010F TCM4300 Data Manual Important Notice Contents Mechanical Data ±1 List of Illustrations List of Tables Introduction FeaturesTCM4300 Functional Block Diagram PZ Package TOP View Pin AssignmentsVSS FmrxenTerminal Description Name Terminal FunctionsDspstrbl DsprwDvdd DvssMTS1 McdsMclkin McrwSint ScenSynclk SyndtaDissipation Rating Table Power Rating Above TA = 25CPackage Derating FactorRecommended Operating Conditions Power ConsumptionReference Characteristics RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Terminal ImpedanceFunction MIN TYP² MAX Unit Parameter Test Conditions MIN TYP MAX UnitParameter MIN TYP MAX Unit Transmit I and Q Channel OutputsAuxiliary D/A Converters Auxiliary D/A Converters Slope AGC, AFC, Pwrcont RSSI/Battery A/D ConverterAuxiliary D/A Converters Slope Lcdcontr Nominal LSB Nominal Output VoltageTransmit TX Channel Frequency Response Digital Mode Transmit TX Channel Frequency Response Analog Mode Page VOH VOL Mclkout Timing Requirements see ±1 and NoteMclkout Mcds Parameter Alternate MIN MAX UnitMcrw MCA4±MCA0 MCD7±MCD0 Mccsh MccslMCA4±MCA0 Parameter Alternate MIN MAX Unit SymbolMCA4±MCA0 MCD7±MCD0 Twdho MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl Motorola 16-Bit Read Cycle, MTS 10 =MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl Mcrw MCA0±MCA410% ThR / W ThWA Dspstrbl DspcslDsprw Dspa Dspd±11. TCM4300 to DSP Interface Write Cycle ±12 Control Signal Analog Mode Digital Mode ±1. TCM4300 Receive Channel Control SignalsMode Fmvox Iqrxen Fmrxen Data Transfer±2. RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Transmit Section ±5. Transmit TX I and Q Channel Outputs Modulation error percentage +100 s %±7. Transmit TX Channel Frequency Response Analog Mode Transmit Burst Operation Digital Mode±6. Transmit TX Channel Frequency Response Digital Mode ±1. Power Ramp-Up/Ramp-Down TIming Diagram Wide-Band Data Demodulator Transmit I And Q Output LevelWide-band Data Interrupts ±8. Typical Bit-Error-Rate Performance Wbdbw =±9. Bits in Control Register WBDCtrl Parameter Test Conditions MIN MAX Unit Mean CNRWBD Wide-band Data Demodulator General Information±11. Auxiliary D /A Converters Slope AGC, AFC, Pwrcont Auxiliary DACs, LCD Contrast Converter±10. Auxiliary D/A Converters ±13. RSSI/Battery A/D Converter RSSI, Battery MonitorTiming And Clock Generation ±12. Auxiliary D /A Converters Slope LcdcontrSpeech-Codec Clock Generation Clock GenerationMicrocontroller Clock Sample Interrupt SintPhase-Adjustment Strategy Mclken RCOMclkin Frequency Synthesizer Interface Highval Clkpol Numclks LowvalMSB/LSB First SyndtaName Description ±14. Synthesizer Control Fields15. External Power Control Signals Power Control PortName Suggested External Application Reset Synclk Syndta SYNLE1 SYNLE0 SynrdyWBD Wbdon Iqrxen Txen ModeOUT1 Fmrxen ScenDint Microcontroller-DSP CommunicationsFifo a Fifo B Cint DSP±16. Microcontroller Register Map Microcontroller Register MapAddr Name Category Wide-Band Data/Control Register±17. Microcontroller Register Definitions ±18. WBDCtrl Register BIT Name Function Reset ValueMicrocontroller Status and Control Registers ±19. MStatCtrl Register Bits LCD ContrastLDC D/A Lcden±21. DSP Register Definitions DSP Register Map±20. DSP Register Map Base Station Offset Register Wide-Band Data RegistersDspcsl TCM4300 Dsprw Dspstrbl Sint Cint Bdint DSP Strb INT±22. DStatCtrl Register Bits DSP Status and Control RegistersPower-On Reset ResetInternal Reset State ±23. Power-On Reset Register Initialization±24. Microcontroller Interface Configuration Intel Microcontroller Mode Of Operation±25. Microcontroller Interface Connections for Intel Mode Microcontroller InterfaceMotorola Microcontroller Mode of Operation Mitsubishi Microcontroller Mode of OperationMcrw Mcds IRQ NMI DintCS3 ±32 PZ S-PQFP-G100 Mechanical DataImportant Notice