Texas Instruments TCM4300 manual Transmit Burst Operation Digital Mode

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Table 4±6. Transmit (TX) Channel Frequency Response (Digital Mode)

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

 

 

 

 

 

0 kHz to 8 kHz (see Note 4)

± 0.3

 

 

 

 

 

 

8 kHz to 15 kHz (see Note 4)

± 0.5

 

 

 

 

 

Frequency response

20 kHz to 45 kHz (see Note 2)

± 29

dB

 

 

45 kHz to 75 kHz (see Note 2)

± 55

 

 

 

 

 

 

 

> 75 kHz (see Note 2)

± 60

 

 

 

 

 

 

Any 30 kHz band centered at > 90 kHz (see Note 2)

± 60

 

 

 

 

 

Peak-to-peak group

0 kHz to 15 kHz

3

μs

delay distortion

 

 

 

 

 

 

 

Absolute channel delay

0 kHz to 15 kHz

320

μs

 

 

 

 

NOTES: 2. Stopband

 

 

 

4. Deviation from ideal 0.35 SQRC response

Table 4±7. Transmit (TX) Channel Frequency Response (Analog Mode)

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

 

 

 

 

 

0 kHz to 8 kHz (see Note 1)

± 0.5

 

 

 

 

 

 

8 kHz to 15 kHz (see Note 1)

± 0.5

 

 

 

 

 

Frequency response

20 kHz to 45 kHz (see Note 2)

± 31

dB

 

 

45 kHz to 75 kHz (see Note 2)

± 70

 

 

 

 

 

 

 

> 75 kHz (see Note 2)

± 70

 

 

 

 

 

 

Any 30 kHz band centered at > 90 kHz (see Note 2)

± 70

 

 

 

 

 

Peak-to-peak group

0 kHz to 15 kHz

3

μs

delay distortion

 

 

 

 

 

 

 

Absolute channel delay

0 kHz to 15 kHz

540

μs

 

 

 

 

NOTES: 1. Ripple magnitude

 

 

2.Stopband

4.4Transmit Burst Operation (Digital Mode)

In the digital mode, the TCM4300 performs all encoding, signal processing, and power ramping for the burst. Start and stop timing of the variable length bursts are set by means of the TXGO bit in the DStatCtrl register. The SINT interrupt output interrupts the DSP at 48.6 kHz which is T/2 interval (T = 1 symbol period = 1/24.3 kHz). The burst is initiated by the DSP writing 1 to 5 dibits to the TXI register, a small positive-delay offset value d to the base station (BST) register, and a 1 to the TXGO bit in the DStatCtrl register.

The TXGO bit is sampled on the falling edge of SINT. The transmit outputs are held at zero differential voltage (each output terminal is held at the voltage supplied to the VCM input terminal) for 9.5 SINT periods (195.5 μs) plus BST offset delay after SINT has detected TXGO high; then the transmit outputs begin to ramp to the initial π /4 DQPSK constellation value. The shape of the ramp is the transient resulting from the internal SQRC filtering. At the same time that the transmit outputs are beginning to ramp, the PAEN digital output goes high. This output can enable the power amplifier of a cellular radio transmitter. The TCM4300 transmit outputs reach the first π /4 DQPSK constellation value (maximum effect point, MEP) 6 SINT periods (3 symbol periods) after the start of the ramp.

The bit stream to be encoded as π /4 DQPSK symbols is generated by right shifts on each SINT of the TXI register with bit 0 (LSB) used first.

Previously written data continues to propagate through the TCM4300 internal filters until the last π /4 DQPSK constellation value (last MEP) occurs at the transmit outputs 15.5 SINT periods (318.9 μs) plus BST offset

4±5

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Contents Data Manual SLWS010F TCM4300 Data Manual Important Notice Contents Mechanical Data ±1 List of Illustrations List of Tables Features IntroductionTCM4300 Functional Block Diagram Pin Assignments PZ Package TOP ViewVSS FmrxenTerminal Functions Terminal Description NameDsprw DspstrblDvdd DvssMcds MTS1Mclkin McrwScen SintSynclk SyndtaPower Rating Above TA = 25C Dissipation Rating TablePackage Derating FactorReference Characteristics Power ConsumptionRecommended Operating Conditions Terminal Impedance RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5Function MIN TYP² MAX Unit Parameter Test Conditions MIN TYP MAX UnitAuxiliary D/A Converters Transmit I and Q Channel OutputsParameter MIN TYP MAX Unit RSSI/Battery A/D Converter Auxiliary D/A Converters Slope AGC, AFC, PwrcontAuxiliary D/A Converters Slope Lcdcontr Nominal LSB Nominal Output VoltageTransmit TX Channel Frequency Response Digital Mode Transmit TX Channel Frequency Response Analog Mode Page Mclkout Mclkout Timing Requirements see ±1 and NoteVOH VOL Parameter Alternate MIN MAX Unit McdsMcrw MCA4±MCA0 MCD7±MCD0 Mccsh MccslParameter Alternate MIN MAX Unit Symbol MCA4±MCA0MCA4±MCA0 MCD7±MCD0 Twdho Motorola 16-Bit Read Cycle, MTS 10 = MCA0±MCA4 MCD0±MCD7 Mccsh MccslMCA0±MCA4 Mcrw MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl10% ThR / W ThWA Dspcsl DspstrblDsprw Dspa Dspd±11. TCM4300 to DSP Interface Write Cycle ±12 ±1. TCM4300 Receive Channel Control Signals Control Signal Analog Mode Digital ModeMode Fmvox Iqrxen Fmrxen Data Transfer ±2. RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Transmit Section Modulation error percentage +100 s % ±5. Transmit TX I and Q Channel Outputs±6. Transmit TX Channel Frequency Response Digital Mode Transmit Burst Operation Digital Mode±7. Transmit TX Channel Frequency Response Analog Mode ±1. Power Ramp-Up/Ramp-Down TIming Diagram Transmit I And Q Output Level Wide-Band Data Demodulator±8. Typical Bit-Error-Rate Performance Wbdbw = Wide-band Data Interrupts±9. Bits in Control Register WBDCtrl Parameter Test Conditions MIN MAX Unit Mean CNRWide-band Data Demodulator General Information WBD±10. Auxiliary D/A Converters Auxiliary DACs, LCD Contrast Converter±11. Auxiliary D /A Converters Slope AGC, AFC, Pwrcont RSSI, Battery Monitor ±13. RSSI/Battery A/D ConverterTiming And Clock Generation ±12. Auxiliary D /A Converters Slope LcdcontrClock Generation Speech-Codec Clock GenerationMicrocontroller Clock Sample Interrupt SintPhase-Adjustment Strategy Mclkin RCOMclken Frequency Synthesizer Interface Clkpol Numclks Lowval HighvalMSB/LSB First Syndta±14. Synthesizer Control Fields Name DescriptionPower Control Port 15. External Power Control SignalsName Suggested External Application Reset Synclk Syndta SYNLE1 SYNLE0 SynrdyIqrxen Txen Mode WBD WbdonOUT1 Fmrxen ScenMicrocontroller-DSP Communications DintFifo a Fifo B Cint DSPMicrocontroller Register Map ±16. Microcontroller Register Map±17. Microcontroller Register Definitions Wide-Band Data/Control RegisterAddr Name Category Microcontroller Status and Control Registers BIT Name Function Reset Value±18. WBDCtrl Register LCD Contrast ±19. MStatCtrl Register BitsLDC D/A Lcden±20. DSP Register Map DSP Register Map±21. DSP Register Definitions Wide-Band Data Registers Base Station Offset RegisterDspcsl TCM4300 Dsprw Dspstrbl Sint Cint Bdint DSP Strb INTDSP Status and Control Registers ±22. DStatCtrl Register BitsReset Power-On ResetInternal Reset State ±23. Power-On Reset Register InitializationIntel Microcontroller Mode Of Operation ±24. Microcontroller Interface Configuration±25. Microcontroller Interface Connections for Intel Mode Microcontroller InterfaceMitsubishi Microcontroller Mode of Operation Motorola Microcontroller Mode of OperationMcrw Mcds IRQ NMI DintCS3 ±32 Mechanical Data PZ S-PQFP-G100Important Notice