Texas Instruments TCM4300 manual Transmit I And Q Output Level, Wide-Band Data Demodulator

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Dibit

In

D Q

	BST Offset		Channel Delay		TXI,
	Delay		(15.5 SINT Periods)		TXQ
	Delay		(15.5 SINT Periods)		TXQ

TXGO

SINT

CLK

DQ

CLK

Delay = 0, 1/4, 1/2, 3/4

BST Offset

Delay

SYNOL

MPAEN

Transmit Channel Delay + d(T/8)

Occurs from last symbol (2 SINT periods) before TXGO goes low

PAEN Delay
9.5	PAEN
19.5

PAEN Delay + d(T/8)

TXGO high: 9.5 SINT periods + d(T/8): PAEN high

TXGO low: 19.5 SINT periods + d(T/8): PAEN low

Figure 4±2. Transmit Power Ramp-Up/Ramp-Down Functional Diagram

4.5Transmit I And Q Output Level

In the digital mode, the output level at TXI and TXQ is controlled by the TCM4300. During the burst, but not including ramp-up or ramp-down periods, the average output level (I2 + Q2)1/2 should approximate the specified value. There is no variable level control for TXI and TXQ within the TCM4300 other than the fixed ramping. In the analog mode, the output of the TCM4300 depends only on the sample values written to the TXI and TXQ registers.

There are small differences in the average output power levels between the digital and the analog modes. These differences require compensation at the system level by a small attenuation in the sample values of the analog output.

When a change in transmit power is necessary, the microcontroller can change the value sent to the PWRCONT DAC, the output of which can be connected to a voltage-controlled attenuator in the transmit path of the RF section.

4.6Wide-Band Data Demodulator

The wide-band data demodulator (WBDD) module demodulates the FM signal and outputs a Manchester-decoded data stream. The WBDD is used for receiving the analog control channels of the forward control channel (FOCC) and the forward voice channel (FVC). The bit error rate (BER) performance requirements are listed in Table 4±8.

4±7

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Contents Data Manual SLWS010F TCM4300 Data Manual Important Notice Contents Mechanical Data ±1 List of Illustrations List of Tables Features IntroductionTCM4300 Functional Block Diagram VSS Pin AssignmentsPZ Package TOP View FmrxenTerminal Functions Terminal Description NameDvdd DsprwDspstrbl DvssMclkin McdsMTS1 McrwSynclk ScenSint SyndtaPackage Power Rating Above TA = 25CDissipation Rating Table Derating FactorPower Consumption Reference CharacteristicsRecommended Operating Conditions Function MIN TYP² MAX Unit Terminal ImpedanceRXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Parameter Test Conditions MIN TYP MAX UnitTransmit I and Q Channel Outputs Auxiliary D/A ConvertersParameter MIN TYP MAX Unit Auxiliary D/A Converters Slope Lcdcontr RSSI/Battery A/D ConverterAuxiliary D/A Converters Slope AGC, AFC, Pwrcont Nominal LSB Nominal Output VoltageTransmit TX Channel Frequency Response Digital Mode Transmit TX Channel Frequency Response Analog Mode Page Mclkout Timing Requirements see ±1 and Note MclkoutVOH VOL Mcrw Parameter Alternate MIN MAX UnitMcds MCA4±MCA0 MCD7±MCD0 Mccsh MccslParameter Alternate MIN MAX Unit Symbol MCA4±MCA0MCA4±MCA0 MCD7±MCD0 Twdho Motorola 16-Bit Read Cycle, MTS 10 = MCA0±MCA4 MCD0±MCD7 Mccsh MccslMCA0±MCA4 Mcrw MCA0±MCA4 MCD0±MCD7 Mccsh Mccsl10% ThR / W ThWA Dsprw DspcslDspstrbl Dspa Dspd±11. TCM4300 to DSP Interface Write Cycle ±12 Mode Fmvox Iqrxen Fmrxen ±1. TCM4300 Receive Channel Control SignalsControl Signal Analog Mode Digital Mode Data Transfer±2. RXIP, RXIN, RXQP, and Rxqn Inputs Avdd = 3 V, 4.5 V, 5 Transmit Section Modulation error percentage +100 s % ±5. Transmit TX I and Q Channel OutputsTransmit Burst Operation Digital Mode ±6. Transmit TX Channel Frequency Response Digital Mode±7. Transmit TX Channel Frequency Response Analog Mode ±1. Power Ramp-Up/Ramp-Down TIming Diagram Transmit I And Q Output Level Wide-Band Data Demodulator±9. Bits in Control Register WBDCtrl ±8. Typical Bit-Error-Rate Performance Wbdbw =Wide-band Data Interrupts Parameter Test Conditions MIN MAX Unit Mean CNRWide-band Data Demodulator General Information WBDAuxiliary DACs, LCD Contrast Converter ±10. Auxiliary D/A Converters±11. Auxiliary D /A Converters Slope AGC, AFC, Pwrcont Timing And Clock Generation RSSI, Battery Monitor±13. RSSI/Battery A/D Converter ±12. Auxiliary D /A Converters Slope LcdcontrMicrocontroller Clock Clock GenerationSpeech-Codec Clock Generation Sample Interrupt SintPhase-Adjustment Strategy RCO MclkinMclken Frequency Synthesizer Interface MSB/LSB First Clkpol Numclks LowvalHighval Syndta±14. Synthesizer Control Fields Name DescriptionName Suggested External Application Reset Power Control Port15. External Power Control Signals Synclk Syndta SYNLE1 SYNLE0 SynrdyOUT1 Iqrxen Txen ModeWBD Wbdon Fmrxen ScenFifo a Fifo B Microcontroller-DSP CommunicationsDint Cint DSPMicrocontroller Register Map ±16. Microcontroller Register MapWide-Band Data/Control Register ±17. Microcontroller Register DefinitionsAddr Name Category BIT Name Function Reset Value Microcontroller Status and Control Registers±18. WBDCtrl Register LDC D/A LCD Contrast±19. MStatCtrl Register Bits LcdenDSP Register Map ±20. DSP Register Map±21. DSP Register Definitions Dspcsl TCM4300 Dsprw Dspstrbl Sint Cint Bdint Wide-Band Data RegistersBase Station Offset Register DSP Strb INTDSP Status and Control Registers ±22. DStatCtrl Register BitsInternal Reset State ResetPower-On Reset ±23. Power-On Reset Register Initialization±25. Microcontroller Interface Connections for Intel Mode Intel Microcontroller Mode Of Operation±24. Microcontroller Interface Configuration Microcontroller InterfaceMcrw Mcds Mitsubishi Microcontroller Mode of OperationMotorola Microcontroller Mode of Operation IRQ NMI DintCS3 ±32 Mechanical Data PZ S-PQFP-G100Important Notice