Silicon Laboratories SI5375 manuals
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Silicon Laboratories SI5375 Manual
180 pages 2.66 Mb
3 Si53xx-RMT ABLE OF C 5 Si53xx-RM7 LIST OF FIGURES10 LIST OF TABLES46 DSPLL48 (BW f 49 f53 Si53xx-RM56 Table 16. SONET Clock Multiplication Settings (FRQTBL=L) (Continued)61 Table 18. SONET to Datacom Clock Multiplication Settings 63 Table 18. SONET to Datacom Clock Multiplication Settings (Continued)64 Table 19. Clock Output Divider Control (DIV34)65 6.2. PLL Self-Calibration67 6.3. Pin Control Input Clock Control70 6.4. Digital Hold/VCO Freeze6.5. Frame Synchronization (Si5366) 71 6.6. Output Phase Adjust (Si5323, Si5366)72 6.7. Output Clock DriversTable 29. FS_OUT Disable Control (DBLFS) Table 30. Output Signal Format Selection (SFOUT) 73 6.8. PLL Bypass Mode6.9. Alarms 75 6.10. Device Reset6.11. DSPLLsim Configuration SoftwareTable 34. Lock Detect Retrigger Time 76 7.1. Clock Multiplication Figure 25. Wideband PLL Divider Settings (Si5325, Si5367) Signal Frequency Limits CKINn 2 kHz710 MHz f32 kHz2 MHz fOSC 4.855.67 GHz fOUT 2 kHz1.475 GHzNote: Fmax= 808 MHz for the Si5327, Si5374 and Si5375 78 Table 36. Dividers and LimitsN2_LS = [2, 4, 6, , 2^20] N3 N3 = N3n N3n = [1,2,3,..,2^19] N3n = [1,2,3,..,2^19] 79 7.2. PLL Self-Calibration81 7.3. Input Clock Configurations (Si5367 and Si5368)7.4. Input Clock ControlFigure 27. Si5324, Si5325, Si5326, Si5327, and Si5374 Input Clock Selection 82 Figure 28. Si5367, Si5368, and Si5369 Input Clock SelectionTable 38. Manual Input Clock Selection (Si5367, Si5368, Si5369) 83 Table 39. Manual Input Clock Selection (Si5324, Si5325, Si5326, Si5374)Table 40. Automatic/Manual Clock Selection 84 Table 41. Input Clock Priority for Auto Switching 7.5. Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374 and Si5375 Free Run Mode 85 Figure 29. Free Run Mode Block Diagram 7.6. Digital HoldFigure 30. Parameters in History Value of M 87 TimeDigital Hold @ t = 0 M M t = HIST_DEL HIST_AVG f 89 freqtime 92 105 Figure 40. CML/LVDS Termination (1.8, 2.5, 3.3V) Figure 41. CMOS Termination (1.8, 2.5, 3.3V) 106 107 8.2. Output Clock Drivers115 8.5. Three-Level (3L) Input Pins (No External Resistors)116 8.6. Three-Level (3L) Input Pins (With External Resistors)Figure 56. Three Level Input Pins 9. Power Supply 117 TQFP PKGQFN PKG119 APPENDIX ANARROWBAND REFERENCESResonator/External Clock SelectionTable 59. Approved Crystals Table 60. XA/XB Reference Sources and Frequencies Fundamental Mode Crystals Reference DriftFigure 59.Typical Reference Jitter Transfer Function Reference Jitter 120 38.88MHz XO, 38.88MHz CKIN, 38.88MHz CKOUT126 APPENDIX CTYPICAL PHASE NOISE PLOTS144 APPENDIX DALARM STRUCTURE147 APPENDIX EINTERNAL PULLUP, PULLDOWN BY PIN154 APPENDIX FTYPICAL PERFORMANCE: BYPASS MODE, PSRR, CROSSTALK, OUTPUT FORMAT JITTER162 APPENDIX GNEAR INTEGER RATIOSInput Frequency Variation = 50 ppmFigure 85. 50 ppm, 2 ppm Steps Test ConditionsScan Ranges and Resolutions: 38.88 MHz External XA-XB ReferenceRMS jitter, fs Figure 86. 200 ppm, 10 ppm Steps Figure 87. 2000 ppm, 50 ppm Steps 38.88 MHz External XA-XB Reference 163 Input Frequency 38.88 MHz External XA-XB Reference Input Frequency Variation = 2000 ppm 164 APPENDIX HJITTER ATTENUATION AND LOOP BWFigure 88. RF Generator, Si5326, Si5324; No Jitter (For Reference) Figure 89. RF Generator, Si5326, Si5324 (50Hz Jitter) 622.08 MHz in, 622.08 MHz out 165 622.08 MHz in, 622.08 MHz outPhase Noise (dBc/Hz) Blue = RF GeneratorFigure 90. RF Generator, Si5326, Si5324 (100Hz Jitter) Figure 91. RF Generator, Si5326, Si5324 (500Hz Jitter) 166 622.08 MHz in, 622.08 MHz outPhase Noise (dBc/Hz)Figure 92. RF Generator, Si5326, Si5324 (1kHz Jitter) Figure 93. RF Generator, Si5326, Si5324 (5kHz Jitter) 167 622.08 MHz in, 622.08 MHz outPhase Noise (dBc/Hz) 622.08 MHz in, 622.08 MHz outPhase Noise (dBc/Hz)Figure 94. RF Generator, Si5326, Si5324 (10kHz Jitter) 168 622.08 MHz in, 622.08 MHz out169 APPENDIX ISi5374 AND Si5375 PCB LAYOUT RECOMMENDATIONS173 APPENDIX JSi5374 AND Si5375 CROSSTALKSi5374, Si5375 Crosstalk Test BedTable 83. Si5374/75 Crosstalk Jitter Values 178 DOCUMENT CHANGE LISTRevision 0.3 to Revision 0.4 Revision 0.4 to Revision 0.41 Revision 0.41 to Revision 0.42 Revision 0.42 to Revision 0.5 180 CONTACT INFORMATION
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