Silicon Laboratories SI5365, SI5369, SI5366, SI5367 16. Si5375, Si5375 Functional Block Diagram

Si53xx-RM

3.16. Si5375

The Si5375 is a highly integrated, 4-PLL jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. Each of the DSPLL® clock multiplier engines accepts an input clock ranging from 2 kHz to 710 MHz and generates an output clock ranging from 2 kHz to 808 MHz. Each DSPLL provides virtually any frequency translation combination across this operating range. For asynchronous, free-running clock generation applications, the Si5375’s reference oscillator can be used as a clock source for any of the four DSPLLs. The Si5375 input clock frequency and clock multiplication ratio are programmable through an I2C interface. The Si5375 is based on Silicon Laboratories' third-generation DSPLL® technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. Each DSPLL loop bandwidth is digitally programmable from 60 Hz to 8 kHz, providing jitter performance optimization at the application level. The device operates from a single 1.8 or 2.5 V supply with on- chip voltage regulators with excellent PSRR. The Si5375 is ideal for providing clock multiplication and jitter attenuation in high port count optical line cards requiring independent timing domains.

	Input Stage	PLL Bypass	Synthesis Stage		Output Stage
CKIN1P_A	÷ N31
CKIN1N_A		Input
		Monitor			PLL Bypass	CKOUT1P_A
		f3		fOSC
			DSPLL®
				÷ NC1_HS	÷ NC1	CKOUT1N_A
			A
	÷ N32
			÷ N2
		PLL Bypass
CKIN1P_B	÷ N31
CKIN1N_B		Input
		Monitor			PLL Bypass	CKOUT1P_B
		f3		fOSC
			DSPLL®
				÷ NC1_HS	÷ NC1	CKOUT1N_B
			B
	÷ N32
			÷ N2
		PLL Bypass
CKIN1P_C	÷ N31
CKIN1N_C		Input
		Monitor		fOSC	PLL Bypass	CKOUT1P_C
		f3	DSPLL®
				÷ NC1_HS	÷ NC1	CKOUT1N_C
			C
	÷ N32
			÷ N2
		PLL Bypass
CKIN1P_D	÷ N31
CKIN1N_D		Input
		Monitor		fOSC	PLL Bypass	CKOUT1P_D
		f3	DSPLL®
				÷ NC1_HS	÷ NC1	CKOUT1N_D
			D
	÷ N32
			÷ N2
RSTL_q	Status / Control				High PSRR	VDD_q
CS_q					Voltage Regulator	GND
		OSC_P/N

SCL SDA LOL_q IRQ_q	Low Jitter
	XO or Clock

Figure 15. Si5375 Functional Block Diagram

Rev. 0.5 31