Silicon Laboratories SI5325, SI5369, SI5365, SI5366 13. Si5369, 14. Si5374/75 Compared to Si5324/19

Si53xx-RM

3.13. Si5369

The Si5369 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps rms jitter performance. The Si5369 accepts four clock inputs ranging from 2 kHz to 710 MHz and generates five independent, synchronous clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The device provides virtually any frequency translation combination across this operating range. The Si5369 input clock frequency and clock multiplication ratio are programmable through an I2C or SPI interface. The DSPLL loop bandwidth is digitally programmable, providing loop bandwidth values as low as 4 Hz. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5369 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. See "7. Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)" on page 76 for a complete description.

RATE[1:0]

Xtal or Refclock

XB

XA

3

BYPASS/DSBL2

2

CKIN_1+

÷ N3_1

1

2

CKOUT_1+

CKIN_1–

fx

÷ NC1

0

CKOUT_1–

CKIN_2+

2

÷ N3_2

f3

CKIN_2–

DSPLL®

fOSC

1

2

CKOUT_2+

CKIN_3+

2

÷ N1_HS

÷ NC2

÷ N3_3

0

CKOUT_2–

CKIN_3–

DSBL2/BYPASS

CKIN_4+

2

÷ N3_4

÷ NC3

1

2

CKOUT_3+

CKIN_4–

0

CKOUT_3–

÷ N2

DSBL34

CKOUT_2

FSYNC

÷ NC4

1

2

CKOUT_4+

CKIN_3

LOGIC/

0

CKOUT_4–

CKIN_4

ALIGN

1 0

C1B

÷ NC5

1

2

CKOUT_5+

C2B

FSYNC

0

CKOUT_5–

C3B

DSBL5

INT_ALM

Control

C1A

C2A

CS0_C3A

VDD

CS1_C4A

LOL

GND

CMODE SDA SDO SCL

SDI

A[2]/SS

A[1:0]

INC DEC FS ALIGN

RST

Figure 13. Si5369 Clock Multiplier and Jitter Attenuator Block Diagram

3.14. Si5374/75 Compared to Si5324/19

In general, the Si5374 can be viewed as a quad version of the Si5324 and the Si5375 can be viewed as a quad version of the Si5319. However, there are not exactly the same. This is an overview of the differences:

1.The Si5374/75 cannot use a crystal as its OSC reference. It requires the use of a single external single-ended or differential crystal oscillator.

2.The Si5374/75 only supports I2C as its serial port protocol and does not have SPI. No I2C address pins are available on the Si5374/75.

3.The Si5374/75 does not provide separate INT_CK1B and CK2B pins to indicate when CKIN1 and CKIN2 do not have valid clock inputs. Instead, the IRQ pin can be programmed to function as one pin, the other pin or both.

4.Selection of the OSC frequency is done by a register (RATE_REG), not by using the RATE pins.

5.The Si5374/75 uses a different version of DSPLLsim: Si537xDSPLLsim.

6.The Si5374/75 does not support 3.3 V operation.

Rev. 0.5 29