Silicon Laboratories SI5327, SI5369, SI5365 SPI Specifications Si5324, Si5325, Si5367, and Si5368

Si53xx-RM

Table 5. DC Characteristics—Microprocessor Devices (Si5324, Si5325, Si5367, Si5368)

Parameter	Symbol	Test Condition	Min	Typ	Max	Units
I2C Bus Lines (SDA, SCL)
Input Voltage Low	VILI2C		—	—	0.25 x VDD	V
Input Voltage High	VIHI2C		0.7 x VDD	—	VDD	V
Input Current	III2C	VIN = 0.1 x VDD	–10	—	10	µA
		to 0.9 x VDD
Hysteresis of Schmitt trig-	VHYSI2C	VDD = 1.8 V	0.1 x VDD	—	—	V
ger inputs
		VDD = 2.5 or 3.3 V	0.05 x VDD	—	—	V
Output Voltage Low	VOHI2C	VDD = 1.8 V	—	—	0.2 x VDD	V
		IO = 3 mA
		VDD = 2.5 or 3.3 V	—	—	0.4	V
		IO = 3 mA

Table 6. SPI Specifications (Si5324, Si5325, Si5367, and Si5368)

Parameter	Symbol	Test Conditions	Min	Typ	Max	Unit
Duty Cycle, SCLK	tDC	SCLK = 10 MHz	40	—	60	%
Cycle Time, SCLK	tc		100	—	—	ns
Rise Time, SCLK	tr	20–80%	—	—	25	ns
Fall Time, SCLK	tf	20–80%	—	—	25	ns
Low Time, SCLK	tlsc	20–20%	30	—	—	ns
High Time, SCLK	thsc	80–80%	30	—	—	ns
Delay Time, SCLK Fall to SDO Active	td1		—	—	25	ns
Delay Time, SCLK Fall to SDO Transition	td2		—	—	25	ns
Delay Time, SS Rise to SDO Tri-state	td3		—	—	25	ns
Setup Time, SS to SCLK Fall	tsu1		25	—	—	ns
Hold Time, SS to SCLK Rise	th1		20	—	—	ns
Setup Time, SDI to SCLK Rise	tsu2		25	—	—	ns
Hold Time, SDI to SCLK Rise	th2		20	—	—	ns
Delay Time between Slave Selects	tcs		25	—	—	ns

Note: All timing is referenced to the 50% level of the waveform unless otherwise noted. Input test levels are VIH = VDD – 4 V, VIL = 0.4 V.

Rev. 0.5 37