Silicon Laboratories SI5316, SI5319, SI5322, SI5323, SI5324, SI5325, SI5326, SI5327, SI5365, SI5366, SI5367, SI5368, SI5369, SI5374, SI5375 - page 34

Si53xx-RM

34 Rev. 0.5

Output Clocks

(CKOUTn—See “8.2. Output Clock Drivers” for Configuring Output Drivers for LVPECL/CML/LVDS/CMOS)

Common Mode VOCM LVPECL 100 

load line-to-line 

VDD –

1.42 —V

DD –

1.25 V

Differential Output

Swing VOD LVPECL 100 

load line-to-line1 1.1 — 1.9 VPP

Single Ended

Output Swing VSE LVPECL 100 

load line-to-line1 0.5 — 0.93 VPP

Differential Output

Voltage CKOVD CML 100  load

line-to-line 350 425 500 mVPP

Common Mode

Output Voltage CKOVCM CML 100  load

line-to-line  —V

DD

– .36 —V

Differential

Output Voltage CKOVD LVDS 100  load

line-to-line 500 700 900 mVPP

Low swing LVDS

100  load

line-to-line

350 425 500 mVPP

Common Mode

Output Voltage CKOVCM LVDS 100  load

line-to-line 

1.125 1.2 1.275 V

Differential Output

Resistance CKORD CML, LVPECL,

LVDS, Disabled,

Sleep

170 200 230 

Output Voltage Low CKO-

VOLLH

CMOS  ——0.4 V

Output Voltage High CKO-

VOHLH

VDD = 1.71 V

CMOS 0.8x

VDD

—— V

Table 4. DC Characteristics (Continued)

Parameter Symbol Test Condition

Si5316

Si5322

Si5324

Si5325

Si5365

Si5366

Si5367

Si5368

Min Typ Max Units

Notes:

1. Refer to Section 6.7.1 and 8.2.1 for restrictions on output formats for TQFP devices at 3.3 V.

2. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 55 on page 115.

3. No under- or overshoot is allowed.

Contents

Main Page Si53xx-RM T ABLE OF C Section Page Page Si53xx-RM Page LIST OF FIGURES Page Page LIST OF TABLES Page 1. Any-Frequency Precision Clock Product Family Overview Page Table 1. Product Selection Guide Table 2. Product Selection Guide (Si5322/25/65/67) 2. Narrowband vs. Wideband Overview 3. Any-Frequency Clock Family Members 3.1. Si5316 Figure 1. Si5316 Any-Frequency Jitter Attenuator Block Diagram DSPLL 3.2. Si5319 Figure 2.Si5319 Any-Frequency Jitter Attenuating Clock Multiplier Block Diagram 3.3. Si5322 Figure 3.Si5322 Low Jitter Clock Multiplier Block Diagram DSPLL 3.4. Si5323 Figure 4.Si5323 Jitter Attenuating Clock Multiplier Block Diagram DSPLL 3.5. Si5324 Figure 5. Si5324 Clock Multiplier and Jitter Attenuator Block Diagram 3.6. Si5325 Figure 6.Si5325 Low Jitter Clock Multiplier Block Diagram 3.7. Si5326 Figure 7. Si5326 Clock Multiplier and Jitter Attenuator Block Diagram 3.8. Si5327 Figure 8.Si5327 Clock Multiplier and Jitter Attenuator Block Diagram 3.9. Si5365 Figure 9.Si5365 Low Jitter Clock Multiplier Block Diagram 3.10. Si5366 Figure 10.Si5366 Jitter Attenuating Clock Multiplier Block Diagram 3.11. Si5367 Figure 11. Si5367 Clock Multiplier Block Diagram 3.12. Si5368 Figure 12.Si5368 Clock Multiplier and Jitter Attenuator Block Diagram 3.13. Si5369 Figure 13.Si5369 Clock Multiplier and Jitter Attenuator Block Diagram 3.14. Si5374/75 Compared to Si5324/19 3.15. Si5374 C D A B 3.16. Si5375 C D A B 4. Device Specifications Figure 16. Differential Voltage Characteristics CKIN, CKOUT Figure 17. Rise/Fall Time Characteristics Table 3. Recommended Operating Conditions Page Page Page Table 5. DC CharacteristicsMicroprocessor Devices (Si5324, Si5325, Si5367, Si5368) Table 6. SPI Specifications (Si5324, Si5325, Si5367, and Si5368) SCLK SS SDI SDO Figure 19. Frame Synchronization Timing Page Page Table 9. Jitter Generation (Si5316, Si5324, Si5366, Si5368) Table 10. Jitter Generation (Si5322, Si5325, Si5365, Si5367) Table 11. Thermal Characteristics 5. DSPLL (All Devices) DSPLL 5.1. Clock Multiplication Figure 21. Clock Multiplication Circuit DSPLL ( BW f f 6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366) 6.1. Clock Multiplication (Si5316, Si5322, Si5323, Si5365, Si5366) Table 12. Si5316, Si5322, Si5323, Si5365 and Si5366 Key Features Table 13. Frequency Settings Page Table 16. SONET Clock Multiplication Settings (FRQTBL=L) Si53xx-RM Page Page Table 16. SONET Clock Multiplication Settings (FRQTBL=L) (Continued) Page Page Page Page Table 18. SONET to Datacom Clock Multiplication Settings Page Table 18. SONET to Datacom Clock Multiplication Settings (Continued) Table 19. Clock Output Divider Control (DIV34) 6.2. PLL Self-Calibration Table 20. Si5316, Si5322, and Si5323 Pins and Reset Table 21. Si5365 and Si5366 Pins and Reset 6.3. Pin Control Input Clock Control Table 22. Manual Input Clock Selection (Si5316, Si5322, Si5323), AUTOSEL= L Table 23. Manual Input Clock Selection (Si5365, Si5366), AUTOSEL= L Table 24. Automatic/Manual Clock Selection Table 25. Clock Active Indicators (AUTOSEL= M or H) (Si5322 and Si5323) Table 26. Clock Active Indicators (AUTOSEL= M or H) (Si5365 and Si5367) Table 27. Input Clock Priority for Auto Switching (Si5322, Si5323) Table 28. Input Clock Priority for Auto Switching (Si5365, Si5366) 6.4. Digital Hold/VCO Freeze 6.5. Frame Synchronization (Si5366) 6.6. Output Phase Adjust (Si5323, Si5366) 6.7. Output Clock Drivers Table 29. FS_OUT Disable Control (DBLFS) Table 30. Output Signal Format Selection (SFOUT) 6.8. PLL Bypass Mode 6.9. Alarms Table 31. DSBL2/BYPASS Pin Settings Table 32. Frequency Offset Control (FOS_CTL) Table 33. Alarm Output Logic Equations 6.10. Device Reset 6.11. DSPLLsim Configuration Software Table 34. Lock Detect Retrigger Time 7.1. Clock Multiplication Figure 25. Wideband PLL Divider Settings (Si5325, Si5367) Page 78 Rev. 0.5 Signal Frequency Limits CKINn 2 kHz710 MHz f32 kHz2 MHz fOSC 4.855.67 GHz fOUT 2 kHz1.475 GHz Note: Fmax= 808 MHz for the Si5327, Si5374 and Si5375 Table 36. Dividers and Limits N2_LS = [2, 4, 6, , 2^20] N3 N3 = N3n N3n = [1,2,3,..,2^19] N3n = [1,2,3,..,2^19] 7.2. PLL Self-Calibration Table 37. CKOUT_ALWAYS_ON and SQ_ICAL Truth Table 7.3. Input Clock Configurations (Si5367 and Si5368) 7.4. Input Clock Control Figure 27. Si5324, Si5325, Si5326, Si5327, and Si5374 Input Clock Selection 82 Rev. 0.5 Figure 28. Si5367, Si5368, and Si5369 Input Clock Selection Table 38. Manual Input Clock Selection (Si5367, Si5368, Si5369) Table 39. Manual Input Clock Selection (Si5324, Si5325, Si5326, Si5374) Table 40. Automatic/Manual Clock Selection Table 41. Input Clock Priority for Auto Switching 7.5. Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374 and Si5375 Free Run Mode Figure 29. Free Run Mode Block Diagram Page 7.6. Digital Hold Figure 30. Parameters in History Value of M Time Digital Hold @ t = 0 M M t = HIST_DEL HIST_AVG Table 42. Digital Hold History Delay Table 43. Digital Hold History Averaging Time Figure 31. Digital Hold vs. VCO Freeze Example f freq time 7.7. Output Phase Adjust (Si5326, Si5368) 7.8. Frame Synchronization Realignment (Si5368 and CK_CONFIG_REG =1) Figure 32. Frame Sync Frequencies Table 44. CKIN3/CKIN4 Frequency Selection (CK_CONF = 1) N1_HS Table 45. Common NC5 Divider Settings Table 46. Alignment Alarm Trigger Threshold Page Table 47. Output Signal Format Selection 7.11. Alarms (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375) Table 48. Loss-of-Signal Validation Times Table 49. Loss-of-Signal Registers Page Figure 33. FOS Compare Table 50. FOS Reference Clock Selection Table 51. CLKnRATE Registers Table 52. Alarm Output Logic Equations (Si5367, Si5368, and Si5369 [CONFIG_REG= 0]) Table 53. Alarm Output Logic Equations [Si5368 and CKCONFIG_REG=1] 7.12. Device Reset Table 54. Lock Detect Retrigger Time (LOCKT) 7.13. I2C Serial Microprocessor Interface Figure 34. I2C Command Format Figure 35. I2C Example Write Command Read Command 7.14. Serial Microprocessor Interface (SPI) Table 55. SPI Command Format Figure 36. SPI Write/Set Address Command Figure 37. SPI Read Command 7.15. Register Descriptions SS SCLK SDI SDO SS SCLK SDI SDO 8. High-Speed I/O 8.1. Input Clock Buffers Figure 39.Single-Ended LVPECL Termination 8.2. Output Clock Drivers Figure 42.Typical Output Circuit (Differential) Table 56. Output Driver Configuration Figure 43. Differential Output Example Requiring Attenuation Figure 44. Typical CMOS Output Circuit (Tie CKOUTn+ and CKOUTn Together) Table 57. Disabling Unused Output Driver Figure 45. CKOUT Structure Table 58. Output Format Measurements Output Disable 100 100 + CKOUT+ CKOUT - Page Page Page Page Page 8.5. Three-Level (3L) Input Pins (No External Resistors) 8.6. Three-Level (3L) Input Pins (With External Resistors) Figure 56. Three Level Input Pins 9. Power Supply TQFP PKG QFN PKG Page APPENDIX ANARROWBAND REFERENCES Resonator/External Clock Selection Table 59. Approved Crystals Table 60. XA/XB Reference Sources and Frequencies Fundamental Mode Crystals 38.88MHz XO, 38.88MHz CKIN, 38.88MHz CKOUT APPENDIX BFREQUENCY PLANS AND JITTER PERFORMANCE (Si5316, Si5319, Si5323, S Introduction High f3 Value Figure 60.Jitter vs. f3 Phase Noise versus f3, 155.52 MHz in, 622.08 MHz out Figure 61.Jitter vs. f3 with FPGA Table 61. Jitter Values for Figure61 38.88 MHz in, 194.4 MHz in, 690.57 MHz out Reference vs. Output Frequency Figure 62. Reference vs. Output Frequency Table 62. Jitter Values for Figure62 155.52 MHz in, 622.08 MHz out, 696.399 MHz out High Reference Frequency Figure 63. Jitter vs. Reference Frequency (1 of 2) 37 MHz thru 163 MHz Ext Ref, 155.52 MHz in, 622.08 MHz out Figure 64. Jitter vs. Reference Frequency (2 of 2) 41 MHz thru 180 MHz Ext Ref, 155.52 MHz in, 622.08 MHz out APPENDIX CTYPICAL PHASE NOISE PLOTS Introduction Page Page Page Page Page Page Page Page Page Page Page Figure 77. 86.685 MHz In; 173.371 MHz and 693.493 MHz Out Table 66. Jitter Values for Figure 77 Red = 693.493 MHz Blue = 173.371 MHz 86.685 MHz in, 173.371 M Hz and 693.493 MHz out Phase Noise (dBc/Hz) Page Page Figure 80. 155.52 MHz and 156.25 MHz In; 622.08 MHz Out Table 67. Jitter Values for Figure 80 Blue = 155.52 MHz Red = 156.25 MHz 155.52 MHz and 156.25M Hz in, 622.08 MH z out Page Digital Video (HD-SDI) 27 MHz in, 148.5 MHz out APPENDIX DALARM STRUCTURE Figure 82. Si5324 and Si5326 Alarm Diagram Figure 83. Si5368 Alarm Diagram (1 of 2) LOS Detector FOS Detector Figure 84. Si5368 Alarm Diagram (2 of 2) APPENDIX EINTERNAL PULLUP, PULLDOWN BY PIN Table 68. Si5316 Pullup/Down Table 69. Si5322 Pullup/Down Table 70. Si5323 Pullup/Down Table 71. Si5319, Si5324, Pullup/Down Table 72. Si5325 Pullup/Down Table 73. Si5326 Pullup/Down Table 74. Si5327 Pullup/Down Table 75. Si5365 Pullup/Down Table 76. Si5366 Pullup/Down Table 77. Si5367 Pullup/Down Table 78. Si5368 Pullup/Down Table 79. Si5369 Pullup/Down Table 80. Si5374/75 Pullup/Down APPENDIX FTYPICAL PERFORMANCE: BYPASS MODE, PSRR, CROSSTALK, OUTPUT FORMAT JITTER Bypass: 622.08 MHz In, 622.08 MHz Out 622.08 MH z in, 622.08 MH z out Power Supply Noise Rejection Power Supply Noise to Output Transfer Function Clock Input Crosstalk Results: Test Conditions Clock Input Crosstalk: Phase Noise Plots Clock Input Crosstalk: Detail View 155.521 MHz in , 622 .084 MHz out Clock Input Crosstalk: Wideband Comparison Clock Input Crosstalk: Output of Rohde and Schwartz RF Rohde and Schwarz: 155.521 MHz Jitter vs. Output Format: 19.44 MHz In, 622.08 MHz Out Spectrum Analyzer: Agilent Model E444OA Table 81. Output Format vs. Jitter 19.44 MHz in, 622.08 MHz out APPENDIX GNEAR INTEGER RATIOS Input Frequency Variation = 50 ppm Figure 85. 50 ppm, 2 ppm Steps Test Conditions Scan Ranges and Resolutions: Input Frequency 38.88 MHz External XA-XB Reference RMS jitter, fs Input Frequency Variation = 2000 ppm APPENDIX HJITTER ATTENUATION AND LOOP BW Figure 88. RF Generator, Si5326, Si5324; No Jitter (For Reference) Figure 89. RF Generator, Si5326, Si5324 (50Hz Jitter) 622.08 MHz in, 622.08 MHz out Phase Noise (dBc/Hz) 622.08 MHz in, 622.08 MHz out Phase Noise (dBc/Hz) Blue = RF Generator Figure 90. RF Generator, Si5326, Si5324 (100Hz Jitter) Figure 91. RF Generator, Si5326, Si5324 (500Hz Jitter) 622.08 MHz in, 622.08 MHz out Phase Noise (dBc/Hz) Figure 92. RF Generator, Si5326, Si5324 (1kHz Jitter) Figure 93. RF Generator, Si5326, Si5324 (5kHz Jitter) 622.08 MHz in, 622.08 MHz out Phase Noise (dBc/Hz) 622.08 MHz in, 622.08 MHz out Phase Noise (dBc/Hz) Figure 94. RF Generator, Si5326, Si5324 (10kHz Jitter) 622.08 MHz in, 622.08 MHz out Phase Noise (dBc/Hz) APPENDIX ISi5374 AND Si5375 PCB LAYOUT RECOMMENDATIONS Page Page Page APPENDIX JSi5374 AND Si5375 CROSSTALK Si5374, Si5375 Crosstalk Test Bed Table 83. Si5374/75 Crosstalk Jitter Values DSPLL Jitter, fsec RMS Page Page Page Page DOCUMENT CHANGE LIST Revision 0.3 to Revision 0.4 Revision 0.4 to Revision 0.41 Revision 0.41 to Revision 0.42 Revision 0.42 to Revision 0.5 Page CONTACT INFORMATION