Silicon Laboratories SI5369, SI5365, SI5366, SI5367 15. Si5374, Si5374 Functional Block Diagram

Si53xx-RM

3.15. Si5374

The Si5374 is a highly integrated, 4-PLL jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. Each of the DSPLL® clock multiplier engines accepts two input clocks ranging from 2 kHz to 710 MHz and generates two independent, synchronous output clocks ranging from 2 kHz to 808 MHz. Each DSPLL provides virtually any frequency translation across this operating range. For asynchronous, free-running clock generation applications, the Si5374’s reference oscillator can be used as a clock source for the four DSPLLs. The Si5374 input clock frequency and clock multiplication ratio are programmable through an I2C interface. The Si5374 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. Each DSPLL loop bandwidth is digitally programmable from 4 to 525 Hz, providing jitter performance optimization at the application level. The device operates from a single 1.8 or 2.5 V supply with on- chip voltage regulators with excellent PSRR. The Si5374 is ideal for providing clock multiplication and jitter attenuation in high port count optical line cards requiring independent timing domains.

	Input Stage	PLL Bypass	Synthesis Stage		Output Stage
CKIN1P_A	÷ N31				PLL Bypass	CKOUT1P_A
CKIN1N_A		Input
		Monitor			÷ NC1	CKOUT1N_A
		f3	DSPLL®
CKIN2P_A				fOSC	÷ NC1_HS
		Hitless	A
CKIN2N_A	÷ N32	Switch			÷ NC2
						CKOUT2P_A
	Internal
	Osc		÷ N2		PLL Bypass	CKOUT2N_A
		PLL Bypass
CKIN3P_B	÷ N31				PLL Bypass	CKOUT3P_B
CKIN3N_B		Input
		Monitor			÷ NC1	CKOUT3N_B
		f3	DSPLL®
CKIN4P_B				fOSC	÷ NC1_HS
		Hitless	B
CKIN4N_B	÷ N32	Switch			÷ NC2
						CKOUT4P_B
	Internal
	Osc		÷ N2		PLL Bypass	CKOUT4N_B
		PLL Bypass
CKIN5P_C	÷ N31				PLL Bypass	CKOUT5P_C
CKIN5N_C		Input
		Monitor			÷ NC1	CKOUT5N_C
		f3	DSPLL®
CKIN6P_C				fOSC	÷ NC1_HS
		Hitless	C
CKIN6N_C	÷ N32	Switch			÷ NC2
						CKOUT6P_C
	Internal
	Osc		÷ N2		PLL Bypass	CKOUT6N_C
		PLL Bypass
CKIN7P_D	÷ N31				PLL Bypass	CKOUT7P_D
CKIN7N_D		Input
		Monitor			÷ NC1	CKOUT7N_D
		f3	DSPLL®
CKIN8P_D				fOSC	÷ NC1_HS
		Hitless	D
CKIN8N_D	÷ N32	Switch			÷ NC2
						CKOUT8P_D
	Internal
	Osc		÷ N2		PLL Bypass	CKOUT8N_D
RSTL_q	Status / Control				High PSRR	VDD_q
CS_q					Voltage Regulator	GND
		OSC_P/N

SCL SDA LOL_q IRQ_q	Low Jitter
	XO or Clock

Figure 14. Si5374 Functional Block Diagram

30 Rev. 0.5