Manuals / Silicon Laboratories / Computer Equipment / Clock

Silicon Laboratories SI5327, SI5369, SI5365, SI5366, SI5367, SI5374 Pin Control Input Clock Control

Models: SI5326 SI5319 SI5369 SI5324 SI5367 SI5322 SI5316 SI5327 SI5366 SI5374 SI5325 SI5323 SI5368 SI5365 SI5375

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Si53xx-RM

6.3. Pin Control Input Clock Control

This section describes the clock selection capabilities (manual input selection, automatic input selection, hitless switching, and revertive switching). When switching between two clocks, LOL may temporarily go high if the two clocks differ in frequency by more than 100 ppm.

6.3.1. Manual Clock Selection

Manual control of input clock selection is chosen via the CS[1:0] pins according to Table 22 and Table 23.

Table 22. Manual Input Clock Selection (Si5316, Si5322, Si5323), AUTOSEL = L

CS (Si5316)	Si5316	Si5322	Si5323
CS_CA (Si5322, Si5323)

0		CKIN1

1		CKIN2

The manual input clock selection settings for the Si5365 and the Si5366 are shown in Table 23. The Si5366 has two modes of operation (See Section “6.5. Frame Synchronization (Si5366)”). With CK_CONF = 0, any of the four input clocks may be selected manually; however, when CK_CONF = 1 the inputs are paired, CKIN1 is paired with CKIN3 and likewise for CKIN2 and CKIN4. Therefore, only two settings are available to select one of the two pairs.

Table 23. Manual Input Clock Selection (Si5365, Si5366), AUTOSEL = L

[CS1_CA4, CS0_CA3]_Pins	Si5365		Si5366

		CK_CONF = 0		CK_CONF = 1
		(5 Output Clocks)		(FS_OUT Configuration)

00	CKIN1	CKIN1		CKIN1/CKIN3

01	CKIN2	CKIN2		CKIN2/CKIN4

10	CKIN3	CKIN3		Reserved

11	CKIN4	CKIN4		Reserved

Notes:

1.To avoid clock switching based on intermediate states during a CS state change, the CS input pins are internally deglitched.

2.If the selected clock enters an alarm condition, the PLL enters digital hold mode.

Rev. 0.5

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Image 67

Silicon Laboratories SI5327 Pin Control Input Clock Control, Manual Input Clock Selection Si5365, Si5366, Autosel = L

Contents

ANY-FREQUENCY Precision Clocks Si53xx-RM Table of Contents Output Clock Drivers High-Speed I/O Si5375 Free Run Mode Si53xx-RM List of Figures Differential Output Example Requiring Attenuation 108 Si53xx-RM List of Tables Si53xx-RM Any-Frequency Precision Clock Product Family Overview Si53xx-RM PLL Product Selection Guide Device Product Selection Guide Si5322/25/65/67Precision Clock Multipliers Wideband Narrowband vs. Wideband Overview Si5316 Any-Frequency Clock Family Members Dspll Si5319 Si5322 Si5322 Low Jitter Clock Multiplier Block Diagram Si5323 Si5323 Jitter Attenuating Clock Multiplier Block Diagram Si5324 Si5324 Clock Multiplier and Jitter Attenuator Block Diagram Si5325 Si5325 Low Jitter Clock Multiplier Block Diagram Si5326 Si5326 Clock Multiplier and Jitter Attenuator Block Diagram Si5327 Si5327 Clock Multiplier and Jitter Attenuator Block Diagram Si5365 Si5365 Low Jitter Clock Multiplier Block Diagram 10. Si5366 Si5366 Jitter Attenuating Clock Multiplier Block Diagram 11. Si5367 Si5367 Clock Multiplier Block Diagram 12. Si5368 Si5368 Clock Multiplier and Jitter Attenuator Block Diagram 14. Si5374/75 Compared to Si5324/19 13. Si5369 15. Si5374 Si5374 Functional Block Diagram 16. Si5375 Si5375 Functional Block Diagram Min Typ Max Unit Device SpecificationsParameter Symbol Test Condition Recommended Operating Conditions1 CKINn Input Pins DC Characteristics Lvpecl 100 Ω Level Input Pins Level Lvcmos Input Pins RST Lvcmos Output Pins Parameter Symbol Test Conditions Min Typ Max Unit SPI Specifications Si5324, Si5325, Si5367, and Si5368 SDO Differential Reference Clock Input Pins XA/XB Frame Synchronization Timing Min Typ Max Units AC Characteristics-All Devices Lvcmos Pins PLL Performance Device Skew Ckopn Jitter Generation Si5322, Si5325, Si5365, Si5367 Jitter Generation Si5316, Si5324, Si5366, Si5368 Parameter Symbol Test Condition Devices Value Unit Thermal Characteristics Dspll All Devices Any-Frequency Precision Clock Dspll Block Diagram Clock Multiplication Circuit Clock Multiplication Jitter Generation PLL PerformanceJitter Transfer Jitter Tolerance Jitter Tolerance Mask/Template Clock Multiplication Si5316, Si5322, Si5323, Si5365, Si5366 Si5316, Si5322, Si5323, Si5365 and Si5366 Key FeaturesFrequency Settings Pin Control Parts Si5316, Si5322, Si5323, Si5365, Si5366 FRQSEL10 Nominal Frequency Values MHz BW10 Input Divider SettingsSi5316 Bandwidth Values CKnDIV N3n Input Divider Ckconf = Sonet Clock Multiplication Settings FRQTBL=LClock Multiplication Si5322, Si5323, Si5365, Si5366 Fsout MHz All Devices Si5366 Only FOUT MHz FIN MHz Mult Factor Mllm Hlll Hhlh Setting Datacom Clock Multiplication Settings Frqtbl = M, Ckconf =MHz Mult Factor OUT* MHz 125 10/8 x 66/64 161.13 173.37 X 64/66 x 237/255 125 Hhhl FIN MHz Mult Factor FOUT* MHz Sonet to Datacom Clock Multiplication Settings 62.500 125 155.520 15625/15552 156.25 Input-to-Output Skew Si5322 and Si5365 Clock Output Divider Control DIV34CKOUT3 and CKOUT4 Si5365 and Si5366 Lock Detect Si5322 and Si5365 PLL Self-Calibration Si5365 and Si5366 Pins and Reset Si5316, Si5322, and Si5323 Pins and Reset Manual Input Clock Selection Si5365, Si5366, Autosel = L Pin Control Input Clock Control Automatic/Manual Clock Selection Clock Active Indicators Autosel = M or H Si5322 and Si5323Clock Active Indicators Autosel = M or H Si5365 and Si5367 Input Clock Priority for Auto Switching Si5322, Si5323 Hitless Switching with Phase Build-Out Si5323, Si5366 Input Clock Priority for Auto Switching Si5365, Si5366 Narrowband Digital Hold Si5316, Si5323, Si5366 Recovery from Digital Hold Si5316, Si5323, Si5366Digital Hold/VCO Freeze Frame Synchronization Si5366 Including Fsync Inputs in Clock Selection Si5366 Output Phase Adjust Si5323, Si5366Using Fsout as a Fifth Output Clock Si5366 Fsync Realignment Si5366 Output Signal Format Selection Sfout Fsout Disable Control DblfsOutput Clock Drivers Alarms PLL Bypass ModeDSBL2/BYPASS Pin Settings Frequency Offset Control Fosctl Alarm Output Logic Equations DSPLLsim Configuration Software Device ResetLock Detect Retrigger Time Wideband PLL Divider Settings Si5325, Si5367 Lock Detect Si5325, Si5367 Loop Bandwidth Si5325, Si5367Input to Output Skew Si5325, Si5367 Dividers and Limits Signal Frequency Limits Low Loop Bandwidth Si5324, Si5327, Si5369, Si5374 Loop Bandwidth Si5319, Si5326, Si5368, Si5375Initiating Internal Self-Calibration Ckoutalwayson and Sqical Truth Table Input Clock Control Input Clock Configurations Si5367 and Si5368 CKIN1,2,3,4 inputs CKIN1,3 & CKIN2,4 clock/FSYNC pairs Manual Input Clock Selection Si5367, Si5368, Si5369Active Input Clock Register Bits Ckselreg or CS pin Active Input Clock Manual Input Clock Selection Si5324, Si5325, Si5326, Si5374 Selected Clock Input Clock Priority for Auto Switching Clock Control Logic in Free Run Mode Free Run Mode Programming Procedure  While in Free Run Free Run Reference Frequency Constraints Parameters in History Value of M Digital Hold Digital Hold History Averaging Time Digital Hold History Delay Digital Hold versus VCO Freeze VCO Freeze Si5319, Si5325, Si5367, Si5375 Fine Skew Control Si5326, Si5368 Output Phase Adjust Si5326, Si5368Unlimited Coarse Skew Adjustment Si5326, Si5368 Coarse Skew Control Si5326, Si5368 Input-to-Output Skew All Devices Frame Synchronization Realignment Si5368 and Ckconfigreg =Output Phase Adjust Si5324, Si5327, Si5369, Si5374 Independent Skew Si5324, Si5326, Si5368, Si5369, Si5374 CKINn Frequency kHz Divisor CKIN3/CKIN4 Frequency Selection Ckconf = Alarm Trigger Threshold Units of T CKOUT2 Common NC5 Divider SettingsAlignment Alarm Trigger Threshold CKOUT2 Frequency MHz NC5 Divider Setting KHz Fsout Fsout Polarity and Pulse Width Control Si5368 Using Fsout as a Fifth Output Clock Si5368Fsync Skew Control Si5368 Including Fsync Inputs in Clock Selection Si5368 Disabling CKOUTn Output Signal Format Selection LOS Selection Loss-of-Signal Validation TimesLoss-of-Signal Registers Clock Validation Time FOS Algorithm Si5324, Si5325, Si5326, Si5368, Si5369, Si5374 Si5326 Si5368 FOS Reference Clock SelectionCLKnRATE Registers FOS Reference Fosen LOS Si5319, Si5375 11.6. C1B, C2B, C3B, Alrmout Si5368 Ckconfigreg = Alarm Output Logic Equations Si5368 and Ckconfigreg = Device Interrupts Lock Detect Retrigger Time Lockt 13. I2C Serial Microprocessor Interface I2C Command Format Serial Microprocessor Interface SPI SPI Command FormatInstructionBYTE0 Address/Data70BYTE1 Register Descriptions Default Device Configuration Input Clock Buffers High-Speed I/O CML/LVDS Termination 1.8, 2.5, 3.3 Typical Output Circuits Output Driver Configuration Output Driver Si5365, Si5366 Si5325, Si5326, Si5367, Si5368 Disabling Unused Output Driver Typical Clock Output Scope Shots Output Format Measurements1,2Name Sfout Pin Sfout Code Single Diff Vocm Vpk-pk Sfout3, lowSwingLVDS Sfout2, Cmos Sfout5, Lvpecl Sfout7, Lvds Cmos External Reference Circuit OSC-P Parameter Symbol Min Max Three-Level 3L Input Pins No External Resistors Three-Level 3L Input Pins With External Resistors Typical Power Supply Bypass Network Tqfp Package Power Supply Packages and Ordering Guide RATE10 Resonator/External Clock SelectionApproved Crystals XA/XB Reference Sources and Frequencies Reference Jitter Fundamental Mode Crystals Reference Drift38.88MHz XO, 38.88MHz CKIN, 38.88MHz Ckout Phase Phase Noise versus f3, 155.52 MHz in, 622.08 MHz outHigh f3 Value DBc/Hz Noise Offset Frequency Hz MHz Out Jitter Bandwidth Yellow, fs RMS Blue, fs RMS Reference vs. Output FrequencyMHz in, 622.08 MHz out, 696.399 MHz out Yellow-696.399 MHz output Blue-622.08 MHz output MHz thru 163 MHz Ext Ref, 155.52 MHz in, 622.08 MHz out High Reference Frequency SONETOC192C, 50 kHz to 80 MHz MHz thru 180 MHz Ext Ref, 155.52 MHz in, 622.08 MHz outSONETOC192A, 20 kHz to 80 MHz SONETOC192B, 4 MHz to 80 MHz Appendix C-TYPICAL Phase Noise Plots 52 MHz In 622.08 MHz Out Loop BW = 7 Hz, Si5324 44 MHz In 156.25 MHz Out Loop BW = 80 Hz 44 MHz In 156.25 MHz Out Loop BW = 5 Hz, Si5324 130 44 MHz In 491.52 MHz Out Loop BW = 7 Hz, Si5324 08 MHz In 672.16 MHz Out Loop BW = 6.9 kHz 08 MHz In 672.16 MHz Out Loop BW = 100 Hz 25 MHz In 155.52 MHz Out Jitter Bandwidth 644.531 MHz Jitter RMS 125 MHz In 644.531 MHz Out Jitter Values for Figure Jitter Bandwidth 690.569 MHz Jitter RMS 125 MHz In 690.569 MHz Out Jitter Values for Figure Jitter Bandwidth 693.493 MHz Jitter RMS 125 MHz In 693.493 MHz Out Jitter Values for Figure Jitter Values for Figure MHz in, 173.371 MHz and 693.493 MHz outDBc/Hz Offset Frequency Hz 685 MHz In 173.371 MHz Out 685 MHz In 693.493 MHz Out DBc/Hz MHz and 156.25MHz in, 622.08 MHz outJitter Bandwidth MHz Input Jitter RMS MHz In 1 GHz Out MHz in, 148.5 MHz out Digital Video HD-SDIJitter Band Appendix D-ALARM Structure Si5368 Alarm Diagram 1 Si5368 Alarm Diagram 2 Pin # Si5322 Pull? Si5316 Pullup/DownSi5322 Pullup/Down Pin # Si5316 Pull? Pin # Si5326 Pull? Si5323 Pullup/DownSi5319, Si5324, Pullup/Down Pin # Si5323 Pull? Si5326 Pullup/Down Si5325 Pullup/DownPin # Si5325 Pull? Pin # Si5365 Pull? Si5327 Pullup/DownSi5365 Pullup/Down Pin # Si5327 Pull? Pin # Si5366 Pull? Si5366 Pullup/Down Pin # Si5368 Pull? Si5367 Pullup/DownSi5368 Pullup/Down Pin # Si5367 Pull? Si5374/75 Pullup/Down Si5369 Pullup/DownPin # Si5374/75 Pull? MHz in, 622.08 MHz out Bypass 622.08 MHz In, 622.08 MHz Out Power Supply Noise to Output Transfer Function Power Supply Noise RejectionMHz in, 155.52 MHz out Bandwidth = 110 Hz Hz loop KHz loop Clock Input Crosstalk Results Test ConditionsJitter Band MHz MHz out 622.084 MHz Out No crosstalk 155.52 MHz 5 .5 2 1 M H z in , 6 2 2 .0 8 4 M H z o u t Clock Input Crosstalk Phase Noise Plots 155 .521 MHz in, 622 .084 MHz ou t Clock Input Crosstalk Detail View 155 .521 M H z in, 622.084 M H z out Clock Input Crosstalk Wideband Comparison Clock Input Crosstalk Output of Rohde and Schwartz RF Hz in, 622.08 M Hz out Jitter vs. Output Format 19.44 MHz In, 622.08 MHz OutSpectrum Analyzer Agilent Model E444OA Output Format vs. Jitter Jitter, fs Test ConditionsInput Frequency Variation = ±50 ppm MHz External XA-XB Reference Input Frequency Variation = ±2000 ppm Input Frequency Fmod Fdev Jitter Start RF Gen Si5326 Si5324 Jitter Values RF Generator, Si5326, Si5324 No Jitter For Reference MHz in, 622.08 MHz out RF Generator, Si5326, Si5324 100 Hz Jitter RF Generator, Si5326, Si5324 1 kHz Jitter RF Generator, Si5326, Si5324 10 kHz Jitter Appendix I-Si5374AND Si5375 PCB Layout Recommendations Ground Plane and Reset Output Clock Routing Oscp Oscn Si5374/75 Crosstalk Jitter Values Si5374, Si5375 Crosstalk Test BedJitter, fsec RMS Si5374, Si5375 Dspll a Si5374, Si5375 Dspll B Si5374, Si5375 Dspll C Si5374, Si5375 Dspll D Revision 0.42 to Revision Revision 0.3 to RevisionRevision 0.4 to Revision Revision 0.41 to Revision Rev 179 Contact Information