Si53xx-RM

3.4. Si5323

The Si5323 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, Fibre Channel, and broadcast video (HD SDI, 3G SDI). The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz and generates two frequency-multiplied clock outputs ranging from 8 kHz to 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, Fibre Channel, and broadcast video rates. The DSPLL loop bandwidth is digitally selectable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or

3.3V supply, the Si5323 is ideal for providing clock multiplication and jitter attenuation in high-performance timing applications. See "6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)" on page 50 for a complete description.

RATE[1:0]

XB

Xtal or Refclock

XA

CKIN_1+

2

 

f3

 

CKIN_1–

 

0

 

 

 

 

 

 

 

 

 

DSPLL®

CKIN_2+

2

1

 

 

CKIN_2–

 

 

 

 

C1B

 

Signal

 

 

C2B

 

Detect

 

 

AUTOSEL

 

 

 

 

LOL

 

 

Bandwidth

 

CS/CA

 

 

 

 

 

Control

 

BWSEL[1:0]

 

 

 

 

 

 

 

FRQTBL

 

Control

 

 

FRQSEL[3:0]

 

 

Frequency

 

INC

 

 

 

 

 

Control

 

DEC

 

 

 

 

 

 

 

RST

 

 

 

 

fOSC

0

1

0

1

2CKOUT_1+ CKOUT_1–

 

 

SFOUT[1:0]

 

2

CKOUT_2+

 

 

 

CKOUT_2–

 

 

DBL2/BY

VDD

GND

Figure 4. Si5323 Jitter Attenuating Clock Multiplier Block Diagram

20

Rev. 0.5

Page 20
Image 20
Silicon Laboratories SI5375, SI5369, SI5365, SI5366, SI5367 manual Si5323 Jitter Attenuating Clock Multiplier Block Diagram