Silicon Laboratories SI5374, SI5369, SI5365, SI5366, SI5367, SI5375 Jitter Tolerance Mask/Template

Si53xx-RM

5.2.3. Jitter Tolerance

Jitter tolerance is defined as the maximum peak-to-peak sinusoidal jitter that can be present on the incoming clock before the DSPLL loses lock. The tolerance is a function of the jitter frequency, because tolerance improves for lower input jitter frequency.

The jitter tolerance of the DSPLL is a function of the loop bandwidth setting. Figure 23 shows the general shape of the jitter tolerance curve versus input jitter frequency. For jitter frequencies above the loop bandwidth, the tolerance is a constant value Aj0. Beginning at the PLL bandwidth, the tolerance increases at a rate of 20 dB/decade for lower input jitter frequencies.

Input	–20 dB/dec.
Jitter
Amplitude		Excessive Input Jitter Range
Aj0
BW/100	BW/10	BW	fJitter In

Figure 23. Jitter Tolerance Mask/Template

The equation for the high frequency jitter tolerance can be expressed as a function of the PLL loop bandwidth (i.e., bandwidth):

5000

Aj0 = ------------ns pk-pk

BW

For example, the jitter tolerance when fin = 155.52 MHz, fout = 622.08 MHz and the loop bandwidth (BW) is 100 Hz:

5000

Aj0 = ------------= 50 ns pk-pk 100

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