Texas Instruments TMS320C6454 manuals
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Texas Instruments TMS320C6454 Warranty
225 pages 1.76 Mb
1 TMS320C6454 Fixed-Point Digital Signal Processor1.1 Features 1.1.1 ZTZ/GTZ BGA Package (Bottom View) 1.2 DescriptionTMS320C6454 Fixed-Point Digital Signal Processor2Submit Documentation FeedbackZTZ/GTZ 697-PIN BALL GRID ARRAY (BGA) PACKAGE (BOTTOM VIEW) 2 TMS320C6454SPRS311A APRIL 2006 REVISED DECEMBER 2006 3 TMS320C6454Fixed-Point Digital Signal Processor1.3 Functional Block DiagramC6454 TMS320C6454 Fixed-Point Digital Signal Processor4Submit Documentation Feedback 4 TMS320C6454Figure 1-2 shows the functional block diagram of the C6454 device. Figure 1-2. Functional Block Diagram 5 TMS320C6454Fixed-Point Digital Signal Processor2 Device Overview2.1 Device Characteristics 6 TMS320C645420 TMS320C645445 TMS320C6454Fixed-Point Digital Signal Processor54 TMS320C645464 TMS320C645465 3.5 Device Status Register Description67 3.6 JTAG ID (JTAGID) Register Description3.7 Pullup/Pulldown ResistorsTable 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued) 69 3.8 Configuration Examples71 4 System Interconnect77 5 C64x+ Megamodule90 6 Device Operating Conditions94 7 C64x+ Peripheral Information and Electrical Specifications7.1 Parameter Information 7.1.2 3.3-V Signal Transition Rates 7.1.1 3.3-V Signal Transition Levels 95 7.1.3 Timing Parameters and Board Routing AnalysisFigure 7-4. Board-Level Input/Output Timings 96 7.3.2 Power-Supply Decoupling7.3.3 Power-Down Operation 97 7.3.4 Preserving Boundary-Scan Functionality on RGMII and DDR2 Memory Pins98 7.4 Enhanced Direct Memory Access (EDMA3) Controller7.4.1 EDMA3 Device-Specific Information 99 7.4.2 EDMA3 Channel Synchronization Events100 7.4.3 EDMA3 Peripheral Register Description(s)112 7.5 Interrupts 7.5.1 Interrupt Sources and Interrupt Controller115 7.5.2 External Interrupts Electrical Data/TimingTable 7-11. Timing Requirements for External Interrupts (see Figure 7-6 ) Figure 7-6. NMI Interrupt Timing 116 7.6 Reset Controller7.6.1 Power-on Reset ( POR Pin) 117 7.6.2 Warm Reset ( RESET Pin)118 7.6.3 System Reset7.6.4 CPU Reset 119 7.6.5 Reset Priority7.6.6 Reset Controller Register 120 7.6.7 Reset Electrical Data/Timing123 7.7 PLL1 and PLL1 Controller124 7.7.1 PLL1 Controller Device-Specific InformationA. DIVIDER D2 and DIVIDER D3 are always enabled. B. CLKIN1 is a 3.3-V signal. 126 7.7.2 PLL1 Controller Memory Map127 7.7.3 PLL1 Controller Register Descriptions137 7.7.4 PLL1 Controller Input and Output Clock Electrical Data/TimingTable 7-29. Timing Requirements for CLKIN1 Devices (see Figure 7-21 ) (see Figure 7-22 ) Figure 7-22. SYSCLK4 Timing 138 7.8 PLL2 and PLL2 Controller138 C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback Figure 7-23. PLL2 Block Diagram 139 7.8.1 PLL2 Controller Device-Specific Information140 7.8.2 PLL2 Controller Memory Map7.8.3 PLL2 Controller Register Descriptions 146 7.8.4 PLL2 Controller Input Clock Electrical Data/TimingTable 7-39. Timing Requirements for CLKIN2 (see Figure 7-30 ) Figure 7-30. CLKIN2 Timing 147 7.9 DDR2 Memory Controller7.9.1 DDR2 Memory Controller Device-Specific Information 148 7.9.2 DDR2 Memory Controller Peripheral Register Description(s)7.9.3 DDR2 Memory Controller Electrical Data/TimingTable 7-40. DDR2 Memory Controller Registers 149 7.10 External Memory Interface A (EMIFA)7.10.1 EMIFA Device-Specific Information 150 7.10.2 EMIFA Peripheral Register Description(s)Table 7-41. EMIFA Registers 151 7.10.3 EMIFA Electrical Data/Timing158 7.10.4 HOLD/ HOLDA TimingTable 7-48. Timing Requirements for the HOLD/ HOLDA Cycles for EMIFA Module (see Figure 7-39 ) (see Figure 7-39 ) Figure 7-39. HOLD/ HOLDA Timing for EMIFA 159 7.10.5 BUSREQ TimingFigure 7-40. BUSREQ Timing for EMIFA 160 7.11 I2C Peripheral 7.11.1 I2C Device-Specific Information162 7.11.2 I2C Peripheral Register Description(s)Table 7-51. I2C Registers 163 7.11.3 I2C Electrical Data/Timing166 7.12 Host-Port Interface (HPI) Peripheral 7.12.1 HPI Device-Specific Information7.12.2 HPI Peripheral Register Description(s) 167 7.12.3 HPI Electrical Data/Timing177 7.13 Multichannel Buffered Serial Port (McBSP)178 7.13.1 McBSP Device-Specific Information180 7.13.2 McBSP Electrical Data/Timing7.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing Table 7-59. Timing Requirements for McBSP Table 7-60. Switching Characteristics Over Recommended Operating Conditions for McBSP (see Figure 7-52 ) 182 Figure 7-52. McBSP Timing182 C64x+ Peripheral Information and Electrical Specifications Submit Documentation Feedback Table 7-61. Timing Requirements for FSR When GSYNC = 1 (see Figure 7-53 )-720 -850NO. UNIT-1000 MIN MAX 1 t Setup time, FSR high before CLKS high 4 ns 2 t Hold time, FSR high after CLKS high 4 ns Figure 7-53. FSR Timing When GSYNC = 1 183 Table 7-62. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0(see Figure 7-54 ) (see Figure 7-54 ) Figure 7-54. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 184 Table 7-64. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0(see Figure 7-55 ) (see Figure 7-55 ) Figure 7-55. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 185 Table 7-66. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1(see Figure 7-56 ) (see Figure 7-56 ) Figure 7-56. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 186 Table 7-68. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1(see Figure 7-57 ) (see Figure 7-57 ) Figure 7-57. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 187 7.14 Ethernet MAC (EMAC)191 7.14.2 EMAC Peripheral Register Description(s)195 7.14.3 EMAC Electrical Data/Timing203 7.14.4 Management Data Input/Output (MDIO)205 7.15 Timers 7.15.1 Timers Device-Specific Information7.15.2 Timers Peripheral Register Description(s)Table 7-93. Timer 1 Registers 206 7.15.3 Timers Electrical Data/TimingTable 7-94. Timing Requirements for Timer Inputs Table 7-95. Switching Characteristics Over Recommended Operating Conditions for Timer Outputs (see Figure 7-73 ) Figure 7-73. Timer Timing 207 7.16 Peripheral Component Interconnect (PCI)7.16.1 PCI Device-Specific Information 208 7.16.2 PCI Peripheral Register Description(s)215 7.17.3 GPIO Electrical Data/TimingTable 7-103. Timing Requirements for GPIO Inputs Table 7-104. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs (see Figure 7-74 ) Figure 7-74. GPIO Port Timing 216 7.18 IEEE 1149.1 JTAG 7.18.1 JTAG Device-Specific Information7.18.2 JTAG Peripheral Register Description(s) 7.18.3 JTAG Electrical Data/TimingTable 7-105. Timing Requirements for JTAG Test Port (see Figure 7-75 ) Figure 7-75. JTAG Test-Port Timing 217 8 Mechanical Data222 PACKAGE OPTION ADDENDUM
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