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Texas Instruments TMS320C6454 warranty Memory Architecture, Aet, Sram, ROM a, Idma

Models: TMS320C6454

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TMS320C6454

Fixed-Point Digital Signal Processor

www.ti.com

SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

5 C64x+ Megamodule

The C64x+ Megamodule consists of several components — the C64x+ CPU, the L1 program and data memory controllers, the L2 memory controller, the internal DMA (IDMA), the interrupt controller, power-down controller, and external memory controller. The C64x+ Megamodule also provides support for memory protection (for L1P, L1D, and L2 memories) and bandwidth management (for resources local to the C64x+ Megamodule). Figure 5-1shows a block diagram of the C64x+ Megamodule.

L1P cache/SRAM

256

L1 program memory controller

L2 memory

256

Cache control

Advanced event

L2

256

Bandwidth management

controller

triggering

cache/

Memory protection

(AET)

SRAM

Cache

256

control

256

256

Bandwidth

C64x+ CPU

Internal

management

Instruction fetch

ROM(A)

Memory

256

SPLOOP buffer

protection

IDMA

16/32−bit instruction dispatch

Instruction decode

128

Data path 1

Data path 2

L1

S1

M1

D1

D2

M2

S2

L2

External memory

xx

xx

xx

xx

controller

To Chip

32

Configuration

A register file

B register file

registers

Registers

128

Slave DMA

256

64

64

Interrupt

L1 data memory controller

and exception

To primary

Cache control

controller

switch

fabric

128

Bandwidth management

Master DMA

256

Power control

Memory protection

32

L1D cache/SRAM

A. When accessing the internal ROM of the DSP, the CPU frequency must always be less than 750 MHz.

PRODUCT PREVIEW

Figure 5-1. 64x+ Megamodule Block Diagram

For more detailed information on the TMS320C64x+ Megamodule on the C6454 device, see the TMS320C64x+ Megamodule Reference Guide (literature number SPRU871).

5.1 Memory Architecture

The TMS320C6454 device contains a 1048KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D).

The L1P memory configuration for the C6454 device is as follows:

∙Region 0 size is 0K bytes (disabled).

∙Region 1 size is 32K bytes with no wait states.

The L1D memory configuration for the C6454 device is as follows:

∙Region 0 size is 0K bytes (disabled).

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C64x+ Megamodule

77

Image 77

Texas Instruments TMS320C6454 warranty Memory Architecture, Aet, Sram, ROM a, Idma

Contents

Features TMS320C6454 Fixed-Point Digital Signal ProcessorZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View 1 ZTZ/GTZ BGA Package Bottom ViewDescription Submit Documentation Feedback Functional Block Diagram Functional Block DiagramTemperature Unless Otherwise Noted ContentsCharacteristics of the C6454 Processor Device CharacteristicsHardware Features C6454CPU DSP Core Description Fixed-Point Digital Signal ProcessorProduct Preview Preview Memory Block Description Block Size Bytes HEX Address Range Memory Map SummaryC6454 Memory Map Summary Ffff 2FFF Ffff3CFF Ffff 4FFF FfffBoot Modes Supported Boot Sequence2 2nd-Level Bootloaders Pin Map Pin AssignmentsC6454 Pin Map Bottom View Quadrant B C6454 Pin Map Bottom View Quadrant C C6454 Pin Map Bottom View Quadrant D Signal Groups Description TINPL1 TOUTL1 TMS320C6454 Fixed-Point Digital Signal ProcessorGpio TOUTL0 TINPL0 SYSCLK4/GP1AACE3A ACE5A ACE4AACE2A ABE7 ABE6 ABE5 ABE4Hpia HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 onlyCLKR1/GP0 Clks SharedRgmdio MdioRgmdclk MdclkPidsel HHWIL/PCLKPCBE3 HR/W/PCBE2 PINTA/GP14 HDS2/PCBE1Terminal Functions Terminal FunctionsName Type 1 IPD/IPUEmifa 64-BIT Control Signals Common to ALL Types of Memory Emifa 64-BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control IPD/IPUEmifa 64-BIT BUS Arbitration AEA1916 Name Emifa 64-BIT AddressAEA15 AEA14Type 1 IPD/IPU 2DESCRIPTION Signal NameAEA6 AEA3Name Emifa 64-BIT Data IPD/IPU Description Name DDR2 Memory Controller 32-BIT Address INTER-INTEGRATED Circuit I2C TimerIPD/IPU Description Name DDR2 Memory Controller 32-BIT Data Multichannel Buffered Serial Port 0 McBSP0 Multichannel Buffered Serial Port 1 McBSP1Management Data INPUT/OUTPUT Mdio for MII/RMII/GMII Management Data INPUT/OUTPUT Mdio for RgmiiReserved for Test Ethernet MAC Emac RgmiiRSV13 RSV12RSV14 RSV15RSV18 RSV17RSV19 RSV20IPD/IPU Description Supply Voltage Monitor PinsSupply Voltage Pins E18 AC6 AC9 AA1 AA6AB7 AE6 AE8 AD5 AD7AF1 CV DDGND Ground PinsF20 F22 F24 G11 G13 G15 G17 G19 G21 G23 M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18 AC7 AC8 AA2 AA7AB6 AE4 AE7 AD6AF2 AH1Development Support DevelopmentDevice Support Device and Development-Support Tool NomenclaturePrefix Temperature RangeDevice Family DeviceProduct Preview C6454 Device Configuration Pins AEA190, ABA10, and Pcien Device Configuration at Device ResetConfiguration IPD PIN AEA15AEA13 AEA14AEA8 AEA6PCI Peripheral Configuration at Device ResetAEA6 PIN AEA8 PIN AEA14 PIN Lower UpperPeripheral States Peripheral Selection After Device ResetMACSEL10 Peripheral Selection Emac Unlock the PERCFG0 register by Using the Perlock register Static Powerdown Reset Enable Progress Disabled EnabledHEX Address Range Acronym Register Name Device State Control RegistersDevice State Control Registers Lockval Peripheral Lock Register DescriptionBit Field Value Description 310 LockvalDescription Peripheral Configuration Register 0 DescriptionBit Field Mode control for I2C DDR2CTL Peripheral Configuration Register 1 DescriptionDDR2CTL Emifactl Peripheral Status Registers Description I2CSTAT Gpiostat TIMER1STAT TIMER0STAT EmacstatHpistat I2CSTAT1715 Pcistat Rmiirst Emac Configuration Register Emaccfg DescriptionEmuctl Emulator Buffer Powerdown Register Emubufpd DescriptionEmifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0 Device Status Register DescriptionSysclkout MCBSP1EN PCI66 Pcieeai MACSEL1 MACSEL0Pcieeai Bit Field Value DescriptionMACSEL10 LendianJtag ID Jtagid Register Description BOOTMODE30Pullup/Pulldown Resistors Variant Part Number Manufacturer LSBProduct Preview Configuration Examples Timers + Emac Gmii + Mdio System Interconnect Internal Buses, Bridges, and Switch FabricsData Switch Fabric Connections TMS320C6454 Switched Central Resource Block DiagramSCR Connection Matrix Configuration Switch FabricC64x+ Megamodule SCR Connection Host Emac Priority AllocationAET Memory ArchitectureSram ROM aTMS320C6454 L1P Memory Configurations TMS320C6454 L2 Memory Configurations Bandwidth Management Memory ProtectionAvailable Memory Page Protection Schemes AID0 BitMegamodule Resets Power-Down ControlMegamodule Reset Global or Local Reset Type MegamoduleVersion Revision a Megamodule RevisionVersion RevisionMegamodule Interrupt Registers C64x+ Megamodule Register DescriptionsMegamodule Idma Registers Megamodule Powerdown Control RegistersMegamodule Revision Register Megamodule Cache Configuration Registers MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff Megamodule L1/L2 Memory Protection Registers L2MPPA4 L2MPPA3L2MPPA5 L2MPPA6HEX Address Range Acronym Register Name Comments 11. Device Configuration Registers Chip-Level Registers10. CPU Megamodule Bandwidth Management Registers Cvdd Recommended Operating ConditionsMIN NOM MAX Unit Recommended Operating ConditionsOH = MAX Parameter Test Conditions MIN TYP MAX UnitII DC TDO DVDD33 = MIN IOL = MAXTDO 2 3.3-V Signal Transition Rates 1 3.3-V Signal Transition LevelsParameter Information Tester Pin ElectronicsTiming Parameters and Board Routing Analysis Power Supplies Recommended Clock and Control Signal Transition BehaviorPower-Supply Sequencing Power-Supply DecouplingProduct Preview EDMA3 Device-Specific Information Enhanced Direct Memory Access EDMA3 ControllerEdma Binary Event Name Event Description Channel EDMA3 Channel Synchronization EventsC6454 EDMA3 Channel Synchronization Events1 EDMA3 Channel Controller Registers EDMA3 Peripheral Register DescriptionsC6454 EDMA3 Channel Synchronization Events DCHMAP33 DCHMAP32DCHMAP34 DCHMAP35Emrh EMREmcr EmcrhQ1E0 Event Queue 1 Entry Register QSTAT1 QSTAT0QSTAT2 QSTAT3EDMA3 Parameter RAM1 EDMA3 Transfer Controller 0 Registers EDMA3 Parameter RAMEDMA3 Transfer Controller 1 Registers EDMA3 Transfer Controller 2 Registers 109 EDMA3 Transfer Controller 3 Registers 111 Interrupt Sources and Interrupt Controller Interrupts10. C6454 DSP Interrupts Event Number Interrupt Event Interrupt SourceTINTHI0 TINTLO0TINTLO1 TINTHI1Idmabuserr L2DMPAIdmacmpa NMI External Interrupts Electrical Data/Timing11. Timing Requirements for External Interrupts1 see Figure Power-on Reset POR Pin Reset Controller12. Reset Types Type InitiatorWarm Reset Reset Pin CPU Reset System ResetReset Type Status Register Description Reset PriorityReset Controller Register 14. Timing Requirements for Reset1 2 3see -8and Figure Reset Electrical Data/Timing720 1000 ParameterTMS320C6454 Power-Up TimingCLKIN1 CLKIN2 POR ResetstatPLL1 and PLL1 Controller Internal Clocks and Maximum Operating Frequencies 1 PLL1 Controller Device-Specific InformationClock Signal MIN MAX Unit 1.3 PLL1 Stabilization, Lock, and Reset Times16. PLL1 Clock Frequency Ranges 1.2 PLL1 Controller Operating Modes18. PLL1 Controller Registers Including Reset Controller 17. PLL1 Stabilization, Lock, and Reset Times2 PLL1 Controller Memory Map MIN TYP3.1 PLL1 Control Register 3 PLL1 Controller Register DescriptionsPllrst Pllpwrdn20. PLL Multiplier Control Register Pllm Field Descriptions PLL Multiplier Control RegisterRatio PLL Pre-Divider Control RegisterPreden D4EN PLL Controller Divider 4 RegisterD5EN PLL Controller Divider 5 RegisterGoset PLL Controller Command RegisterGostat PLL Controller Status RegisterPLL Controller Clock Align Control Register SYS5 Plldiv Ratio Change Status RegisterSYS5 SYS4 SYS5ON SYS4ON SYS3ON SYS2ON Sysclk Status Register720 850 1000 29. Timing Requirements for CLKIN1 Devices1 2 3 see FigurePLL Modes Unit X1 Bypass X20, x25, x30PLL2 and PLL2 Controller 31. PLL2 Clock Frequency Ranges 1 PLL2 Controller Device-Specific Information1.2 PLL2 Controller Operating Modes Pllref Pllen =3 PLL2 Controller Register Descriptions 2 PLL2 Controller Memory Map32. PLL2 Controller Registers HEX Address Range Acronym DescriptionD1EN PLL Controller Divider 1 RegisterPLL Controller Command Register ALN1 SYS1 SYS1ON 39. Timing Requirements for CLKIN21 2 3 see Figure 4 PLL2 Controller Input Clock Electrical Data/Timing1 DDR2 Memory Controller Device-Specific Information DDR2 Memory Controller40. DDR2 Memory Controller Registers 2 DDR2 Memory Controller Peripheral Register Descriptions3 DDR2 Memory Controller Electrical Data/Timing Emifa Device-Specific Information External Memory Interface a Emifa41. Emifa Registers Emifa Peripheral Register DescriptionsAeclkin Emifa Electrical Data/Timing42. Timing Requirements for Aeclkin for EMIFA1 2 see Figure 720 850 1000UNIT 720Aeclkin AECLKOUT1 ACEx ABE70 Setup = Hold =ABA10 AED630 Read Data AAOE/ASOE a AAWE/ASWE a AR/W Aardy B DeassertedAeclkout Aardya Asserted Deasserted Strobe Setup = Extended StrobeABA10 AED630 155 AEA190/ABA10 BE1 BE2 BE3 BE4EA1 EA2 EA3 EA4 ASADS/ASREB AAOE/ASOEB AAWE/ASWEBWrite Latency = HHOLDAL-HOLDL Hold time, Hold low after Holda low HOLD/HOLDA TimingDSP Owns Bus Hold HoldaBusreq Timing Delay time, Aeclkout high to Abusreq valid AECLKOUTx11.1 I2C Device-Specific Information 11 I2C PeripheralSCL I2COARI2CCLKH I2CSAR I2CXSR51. I2C Registers 11.2 I2C Peripheral Register Descriptions11.3 I2C Electrical Data/Timing Standard Mode Fast Mode MIN MAXUnit MAX SDA SCLStop Start Repeated Start Stop Stop StartHPI Device-Specific Information Host-Port Interface HPI PeripheralHPI Peripheral Register Descriptions 54. HPI Control RegistersHPI Electrical Data/Timing See -56through Figure HCNTL10 HCS HasHR/W Hhwil Hstrobea HD150Hrdyb HR/W Hhwil Hstrobe a46. HPI16 Write Timing has Not Used, Tied High 47. HPI16 Write Timing has Used HCS input HD310 output Hrdyb output Has input HCNTL10 input HR/W input49. HPI32 Read Timing has Used Input HCS input 50. HPI32 Write Timing has Not Used, Tied HighInput HCS input HD310 input 51. HPI32 Write Timing has UsedMultichannel Buffered Serial Port McBSP McBSP Device-Specific Information 58. McBSP 1 Registers Product McBSP Electrical Data/Timing181 Clks Clks ClkrClkx Clkx FSX Master Slave MIN MAXSlave MIN MAX Master Slave MIN Hold time, DR valid after Clkx high + 36P Setup time, DR valid before Clkx high 18P186 Ethernet Bus Ethernet MAC EmacInterface Modes Emac Device-Specific InformationRmii 70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii ModesBall Number Device PIN Name Interface Mode Clocking 71. Ethernet MAC Emac Control Registers Emac Peripheral Register DescriptionsSoftreset MacconfigRX5FREEBUFFER RX6FREEBUFFERHEX Address Range Acronym 72. Emac Statistics Registers02C8 2000 02C8 3FFF Emac Descriptor Memory 73. Emac Control Module Registers74. Emac Descriptor Memory Mtclk Emac Electrical Data/Timing1000 Mbps 100/10 Mbps Output 720 1000UNIT 1000 MbpsMrclk Input MRXD7−MRXD4GMII only MRXD3−MRXD0MTXD7−MTXD0 MTXD3−MTXD0NO.PARAMETER Rmrefclk Emac Rmii Electrical Data/TimingMrxer Inputs 720 1000 Rmrefclk InputMRXD1-MRXD0 Mcrsdv Output Emac Rgmii Electrical Data/Timing201 70. Emac Transmit Interface Timing Rgmii OperationAB Mdio Peripheral Register Descriptions 89. Mdio Registers Management Data Input/Output MdioMdio Device-Specific Information Mdio output Delay time, Mdclk low to Mdio data output valid 100Mdio input Timers Device-Specific Information TimersTimers Peripheral Register Descriptions 92. Timer 0 RegistersTINPLx TOUTLx Timers Electrical Data/Timing94. Timing Requirements for Timer Inputs1 see Figure Register Default Value 96. Default Values for PCI Configuration RegistersPeripheral Component Interconnect PCI PCI Device-Specific InformationPCI Peripheral Register Descriptions 97. PCI Configuration Registers98. PCI Back End Configuration Registers 99. DSP-toPCI Address Translation Registers HEX Address Offset Acronym Register Name 100. PCI Hook Configuration Registers101. PCI External Memory Space 48FF Ffff 47FF Ffff49FF Ffff 4A7F FfffPCI Electrical Data/Timing Gpio Device-Specific Information General-Purpose Input/Output GpioGpio Peripheral Register Descriptions 102. Gpio RegistersGPIx GPOx Gpio Electrical Data/Timing103. Timing Requirements for Gpio Inputs1 2 see Figure Jtag Device-Specific Information Ieee 1149.1 JtagIeee 1149.1 Jtag Compatibility Statement 105. Timing Requirements for Jtag Test Port see FigureThermal Data Thermal Resistance Characteristics S-PBGA Package ZTZ/GTZPackaging Information AIR FlowSee ADDITIONS/MODIFICATIONS/DELETIONS Revision HistoryC6454 Revision History Changed -4title to EDMA3 Channel Controller Registers Product Preview Revision History 221 Eco Plan Orderable Device Status PackageMSL Peak Temp QtyPage Page Important Notice