Texas Instruments TMS320C6454 warranty Contents, Temperature Unless Otherwise Noted

TMS320C6454

Fixed-Point Digital Signal Processor

www.ti.com

SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

Contents

1 TMS320C6454 Fixed-Point Digital Signal
	Processor		1
	1.1	Features	1
	1.1.1 ZTZ/GTZ BGA Package (Bottom View)		2
	1.2	Description	2
	1.3	Functional Block Diagram	4
2	Device Overview		6
	2.1	Device Characteristics	6
	2.2	CPU (DSP Core) Description	7
	2.3	Memory Map Summary	10
	2.4	Boot Sequence	12
	2.5	Pin Assignments	14
	2.6	Signal Groups Description	18
	2.7	Terminal Functions	24
	2.8	Development	47
3	Device Configuration		50
	3.1	Device Configuration at Device Reset	50
	3.2	Peripheral Configuration at Device Reset	52
	3.3	Peripheral Selection After Device Reset	53
	3.4	Device State Control Registers	55
	3.5	Device Status Register Description	65
	3.6	JTAG ID (JTAGID) Register Description	67
	3.7	Pullup/Pulldown Resistors	67
	3.8	Configuration Examples	69
4	System Interconnect		71
	4.1	Internal Buses, Bridges, and Switch Fabrics	71
	4.2	Data Switch Fabric Connections	72
	4.3	Configuration Switch Fabric	74
	4.4	Priority Allocation	76
5	C64x+ Megamodule		77
	5.1	Memory Architecture	77
	5.2	Memory Protection	80
	5.3	Bandwidth Management	80
	5.4	Power-Down Control	81

5.5	Megamodule Resets	81
5.6	Megamodule Revision	82
5.7	C64x+ Megamodule Register Description(s)	83
6 Device Operating Conditions		90

6.1Absolute Maximum Ratings Over Operating Case

Temperature Range (Unless Otherwise Noted)	90
6.2 Recommended Operating Conditions	90

6.3Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case

Temperature (Unless Otherwise Noted)	92
7 C64x+ Peripheral Information and Electrical
Specifications	94
7.1 Parameter Information	94

7.2Recommended Clock and Control Signal Transition

Behavior	96
7.3 Power Supplies	96

7.4Enhanced Direct Memory Access (EDMA3)

		Controller	98
7.5		Interrupts	112
7.6		Reset Controller	116
7.7	PLL1 and PLL1 Controller		123
7.8	PLL2 and PLL2 Controller		138
7.9		DDR2 Memory Controller	147
7.10		External Memory Interface A (EMIFA)	149
7.11		I2C Peripheral	160
7.12		Host-Port Interface (HPI) Peripheral	166
7.13		Multichannel Buffered Serial Port (McBSP)	177
7.14		Ethernet MAC (EMAC)	187
7.15		Timers	205
7.16		Peripheral Component Interconnect (PCI)	207
7.17		General-Purpose Input/Output (GPIO)	214
7.18		IEEE 1149.1 JTAG	216
8 Mechanical Data			217
8.1		Thermal Data	217
8.2		Packaging Information	217
Revision History			218

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