Features
TMS320C6454 Fixed-Point Digital Signal Processor
ZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View
1 ZTZ/GTZ BGA Package Bottom View
Description
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Functional Block Diagram
Functional Block Diagram
Temperature Unless Otherwise Noted
Contents
Characteristics of the C6454 Processor
Device Characteristics
Hardware Features
C6454
CPU DSP Core Description
Fixed-Point Digital Signal Processor
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Preview
Memory Block Description Block Size Bytes HEX Address Range
Memory Map Summary
C6454 Memory Map Summary
Ffff
2FFF Ffff
3CFF Ffff
4FFF Ffff
Boot Modes Supported
Boot Sequence
2 2nd-Level Bootloaders
Pin Map
Pin Assignments
C6454 Pin Map Bottom View Quadrant B
C6454 Pin Map Bottom View Quadrant C
C6454 Pin Map Bottom View Quadrant D
Signal Groups Description
TINPL1 TOUTL1
TMS320C6454 Fixed-Point Digital Signal Processor
Gpio TOUTL0 TINPL0
SYSCLK4/GP1A
ACE3A
ACE5A ACE4A
ACE2A
ABE7 ABE6 ABE5 ABE4
Hpia
HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 only
CLKR1/GP0
Clks Shared
Rgmdio
Mdio
Rgmdclk
Mdclk
Pidsel
HHWIL/PCLK
PCBE3
HR/W/PCBE2 PINTA/GP14 HDS2/PCBE1
Terminal Functions
Terminal Functions
Name
Type 1 IPD/IPU
Emifa 64-BIT Control Signals Common to ALL Types of Memory
Emifa 64-BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control
IPD/IPU
Emifa 64-BIT BUS Arbitration
AEA1916
Name Emifa 64-BIT Address
AEA15
AEA14
Type 1 IPD/IPU 2DESCRIPTION
Signal Name
AEA6
AEA3
Name Emifa 64-BIT Data
IPD/IPU Description Name
DDR2 Memory Controller 32-BIT Address
INTER-INTEGRATED Circuit I2C
Timer
IPD/IPU Description Name DDR2 Memory Controller 32-BIT Data
Multichannel Buffered Serial Port 0 McBSP0
Multichannel Buffered Serial Port 1 McBSP1
Management Data INPUT/OUTPUT Mdio for MII/RMII/GMII
Management Data INPUT/OUTPUT Mdio for Rgmii
Reserved for Test
Ethernet MAC Emac Rgmii
RSV13
RSV12
RSV14
RSV15
RSV18
RSV17
RSV19
RSV20
IPD/IPU Description
Supply Voltage Monitor Pins
Supply Voltage Pins
E18
AC6 AC9
AA1 AA6
AB7
AE6 AE8
AD5 AD7
AF1
CV DD
GND
Ground Pins
F20 F22 F24 G11 G13 G15 G17 G19 G21 G23
M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18
AC7 AC8
AA2 AA7
AB6
AE4 AE7
AD6
AF2
AH1
Development Support
Development
Device Support
Device and Development-Support Tool Nomenclature
Prefix
Temperature Range
Device Family
Device
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C6454 Device Configuration Pins AEA190, ABA10, and Pcien
Device Configuration at Device Reset
Configuration IPD PIN
AEA15
AEA13
AEA14
AEA8
AEA6
PCI
Peripheral Configuration at Device Reset
AEA6 PIN AEA8 PIN AEA14 PIN
Lower Upper
Peripheral States
Peripheral Selection After Device Reset
MACSEL10 Peripheral Selection Emac
Unlock the PERCFG0 register by Using the Perlock register
Static Powerdown Reset Enable Progress Disabled Enabled
HEX Address Range Acronym Register Name
Device State Control Registers
Device State Control Registers
Lockval
Peripheral Lock Register Description
Bit Field Value Description 310
Lockval
Description
Peripheral Configuration Register 0 Description
Bit Field
Mode control for I2C
DDR2CTL
Peripheral Configuration Register 1 Description
DDR2CTL Emifactl
Peripheral Status Registers Description
I2CSTAT Gpiostat TIMER1STAT TIMER0STAT Emacstat
Hpistat
I2CSTAT
1715
Pcistat
Rmiirst
Emac Configuration Register Emaccfg Description
Emuctl
Emulator Buffer Powerdown Register Emubufpd Description
Emifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0
Device Status Register Description
Sysclkout MCBSP1EN PCI66
Pcieeai MACSEL1 MACSEL0
Pcieeai
Bit Field Value Description
MACSEL10
Lendian
Jtag ID Jtagid Register Description
BOOTMODE30
Pullup/Pulldown Resistors
Variant Part Number Manufacturer LSB
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Configuration Examples
Timers + Emac Gmii + Mdio
System Interconnect
Internal Buses, Bridges, and Switch Fabrics
Data Switch Fabric Connections
TMS320C6454
Switched Central Resource Block Diagram
SCR Connection Matrix
Configuration Switch Fabric
C64x+ Megamodule SCR Connection
Host Emac
Priority Allocation
AET
Memory Architecture
Sram
ROM a
TMS320C6454 L1P Memory Configurations
TMS320C6454 L2 Memory Configurations
Bandwidth Management
Memory Protection
Available Memory Page Protection Schemes
AID0 Bit
Megamodule Resets
Power-Down Control
Megamodule Reset Global or Local
Reset Type Megamodule
Version Revision a
Megamodule Revision
Version
Revision
Megamodule Interrupt Registers
C64x+ Megamodule Register Descriptions
Megamodule Idma Registers
Megamodule Powerdown Control Registers
Megamodule Revision Register
Megamodule Cache Configuration Registers
MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff
Megamodule L1/L2 Memory Protection Registers
L2MPPA4
L2MPPA3
L2MPPA5
L2MPPA6
HEX Address Range Acronym Register Name Comments
11. Device Configuration Registers Chip-Level Registers
10. CPU Megamodule Bandwidth Management Registers
Cvdd
Recommended Operating Conditions
MIN NOM MAX Unit
Recommended Operating Conditions
OH = MAX
Parameter Test Conditions MIN TYP MAX Unit
II DC
TDO DVDD33 = MIN IOL = MAX
TDO
2 3.3-V Signal Transition Rates
1 3.3-V Signal Transition Levels
Parameter Information
Tester Pin Electronics
Timing Parameters and Board Routing Analysis
Power Supplies
Recommended Clock and Control Signal Transition Behavior
Power-Supply Sequencing
Power-Supply Decoupling
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EDMA3 Device-Specific Information
Enhanced Direct Memory Access EDMA3 Controller
Edma Binary Event Name Event Description Channel
EDMA3 Channel Synchronization Events
C6454 EDMA3 Channel Synchronization Events1
EDMA3 Channel Controller Registers
EDMA3 Peripheral Register Descriptions
C6454 EDMA3 Channel Synchronization Events
DCHMAP33
DCHMAP32
DCHMAP34
DCHMAP35
Emrh
EMR
Emcr
Emcrh
Q1E0 Event Queue 1 Entry Register
QSTAT1
QSTAT0
QSTAT2
QSTAT3
EDMA3 Parameter RAM1
EDMA3 Transfer Controller 0 Registers
EDMA3 Parameter RAM
EDMA3 Transfer Controller 1 Registers
EDMA3 Transfer Controller 2 Registers
109
EDMA3 Transfer Controller 3 Registers
111
Interrupt Sources and Interrupt Controller
Interrupts
10. C6454 DSP Interrupts
Event Number Interrupt Event Interrupt Source
TINTHI0
TINTLO0
TINTLO1
TINTHI1
Idmabuserr
L2DMPA
Idmacmpa
NMI
External Interrupts Electrical Data/Timing
11. Timing Requirements for External Interrupts1 see Figure
Power-on Reset POR Pin
Reset Controller
12. Reset Types
Type Initiator
Warm Reset Reset Pin
CPU Reset
System Reset
Reset Type Status Register Description
Reset Priority
Reset Controller Register
14. Timing Requirements for Reset1 2 3see -8and Figure
Reset Electrical Data/Timing
720 1000
Parameter
TMS320C6454
Power-Up Timing
CLKIN1 CLKIN2 POR
Resetstat
PLL1 and PLL1 Controller
Internal Clocks and Maximum Operating Frequencies
1 PLL1 Controller Device-Specific Information
Clock Signal MIN MAX Unit
1.3 PLL1 Stabilization, Lock, and Reset Times
16. PLL1 Clock Frequency Ranges
1.2 PLL1 Controller Operating Modes
18. PLL1 Controller Registers Including Reset Controller
17. PLL1 Stabilization, Lock, and Reset Times
2 PLL1 Controller Memory Map
MIN TYP
3.1 PLL1 Control Register
3 PLL1 Controller Register Descriptions
Pllrst
Pllpwrdn
20. PLL Multiplier Control Register Pllm Field Descriptions
PLL Multiplier Control Register
Ratio
PLL Pre-Divider Control Register
Preden
D4EN
PLL Controller Divider 4 Register
D5EN
PLL Controller Divider 5 Register
Goset
PLL Controller Command Register
Gostat
PLL Controller Status Register
PLL Controller Clock Align Control Register
SYS5
Plldiv Ratio Change Status Register
SYS5 SYS4
SYS5ON SYS4ON SYS3ON SYS2ON
Sysclk Status Register
720 850 1000
29. Timing Requirements for CLKIN1 Devices1 2 3 see Figure
PLL Modes Unit
X1 Bypass X20, x25, x30
PLL2 and PLL2 Controller
31. PLL2 Clock Frequency Ranges
1 PLL2 Controller Device-Specific Information
1.2 PLL2 Controller Operating Modes
Pllref Pllen =
3 PLL2 Controller Register Descriptions
2 PLL2 Controller Memory Map
32. PLL2 Controller Registers
HEX Address Range Acronym Description
D1EN
PLL Controller Divider 1 Register
PLL Controller Command Register
ALN1
SYS1
SYS1ON
39. Timing Requirements for CLKIN21 2 3 see Figure
4 PLL2 Controller Input Clock Electrical Data/Timing
1 DDR2 Memory Controller Device-Specific Information
DDR2 Memory Controller
40. DDR2 Memory Controller Registers
2 DDR2 Memory Controller Peripheral Register Descriptions
3 DDR2 Memory Controller Electrical Data/Timing
Emifa Device-Specific Information
External Memory Interface a Emifa
41. Emifa Registers
Emifa Peripheral Register Descriptions
Aeclkin
Emifa Electrical Data/Timing
42. Timing Requirements for Aeclkin for EMIFA1 2 see Figure
720 850 1000UNIT
720
Aeclkin AECLKOUT1
ACEx ABE70
Setup = Hold =
ABA10 AED630 Read Data
AAOE/ASOE a AAWE/ASWE a AR/W Aardy B Deasserted
Aeclkout Aardya Asserted Deasserted
Strobe Setup = Extended Strobe
ABA10 AED630
155
AEA190/ABA10
BE1 BE2 BE3 BE4
EA1 EA2 EA3 EA4
ASADS/ASREB AAOE/ASOEB AAWE/ASWEB
Write Latency =
HHOLDAL-HOLDL Hold time, Hold low after Holda low
HOLD/HOLDA Timing
DSP Owns Bus
Hold Holda
Busreq Timing
Delay time, Aeclkout high to Abusreq valid AECLKOUTx
11.1 I2C Device-Specific Information
11 I2C Peripheral
SCL
I2COAR
I2CCLKH I2CSAR
I2CXSR
51. I2C Registers
11.2 I2C Peripheral Register Descriptions
11.3 I2C Electrical Data/Timing
Standard Mode Fast Mode MIN MAX
Unit MAX
SDA SCL
Stop Start Repeated
Start Stop
Stop Start
HPI Device-Specific Information
Host-Port Interface HPI Peripheral
HPI Peripheral Register Descriptions
54. HPI Control Registers
HPI Electrical Data/Timing
See -56through Figure
HCNTL10
HCS Has
HR/W Hhwil Hstrobea
HD150
Hrdyb
HR/W Hhwil Hstrobe a
46. HPI16 Write Timing has Not Used, Tied High
47. HPI16 Write Timing has Used
HCS input HD310 output Hrdyb output
Has input HCNTL10 input HR/W input
49. HPI32 Read Timing has Used
Input HCS input
50. HPI32 Write Timing has Not Used, Tied High
Input HCS input HD310 input
51. HPI32 Write Timing has Used
Multichannel Buffered Serial Port McBSP
McBSP Device-Specific Information
58. McBSP 1 Registers
Product
McBSP Electrical Data/Timing
181
Clks
Clks Clkr
Clkx
Clkx FSX
Master Slave MIN MAX
Slave MIN MAX
Master Slave MIN
Hold time, DR valid after Clkx high + 36P
Setup time, DR valid before Clkx high 18P
186
Ethernet Bus
Ethernet MAC Emac
Interface Modes
Emac Device-Specific Information
Rmii
70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii Modes
Ball Number Device PIN Name
Interface Mode Clocking
71. Ethernet MAC Emac Control Registers
Emac Peripheral Register Descriptions
Softreset
Macconfig
RX5FREEBUFFER
RX6FREEBUFFER
HEX Address Range Acronym
72. Emac Statistics Registers
02C8 2000 02C8 3FFF Emac Descriptor Memory
73. Emac Control Module Registers
74. Emac Descriptor Memory
Mtclk
Emac Electrical Data/Timing
1000 Mbps 100/10 Mbps
Output 720 1000UNIT 1000 Mbps
Mrclk Input MRXD7−MRXD4GMII only
MRXD3−MRXD0
MTXD7−MTXD0
MTXD3−MTXD0
NO.PARAMETER
Rmrefclk
Emac Rmii Electrical Data/Timing
Mrxer Inputs 720 1000
Rmrefclk Input
MRXD1-MRXD0 Mcrsdv
Output
Emac Rgmii Electrical Data/Timing
201
70. Emac Transmit Interface Timing Rgmii OperationAB
Mdio Peripheral Register Descriptions 89. Mdio Registers
Management Data Input/Output Mdio
Mdio Device-Specific Information
Mdio output
Delay time, Mdclk low to Mdio data output valid 100
Mdio input
Timers Device-Specific Information
Timers
Timers Peripheral Register Descriptions
92. Timer 0 Registers
TINPLx TOUTLx
Timers Electrical Data/Timing
94. Timing Requirements for Timer Inputs1 see Figure
Register Default Value
96. Default Values for PCI Configuration Registers
Peripheral Component Interconnect PCI
PCI Device-Specific Information
PCI Peripheral Register Descriptions
97. PCI Configuration Registers
98. PCI Back End Configuration Registers
99. DSP-toPCI Address Translation Registers
HEX Address Offset Acronym Register Name
100. PCI Hook Configuration Registers
101. PCI External Memory Space
48FF Ffff
47FF Ffff
49FF Ffff
4A7F Ffff
PCI Electrical Data/Timing
Gpio Device-Specific Information
General-Purpose Input/Output Gpio
Gpio Peripheral Register Descriptions
102. Gpio Registers
GPIx GPOx
Gpio Electrical Data/Timing
103. Timing Requirements for Gpio Inputs1 2 see Figure
Jtag Device-Specific Information
Ieee 1149.1 Jtag
Ieee 1149.1 Jtag Compatibility Statement
105. Timing Requirements for Jtag Test Port see Figure
Thermal Data
Thermal Resistance Characteristics S-PBGA Package ZTZ/GTZ
Packaging Information
AIR Flow
See ADDITIONS/MODIFICATIONS/DELETIONS
Revision History
C6454 Revision History
Changed -4title to EDMA3 Channel Controller Registers
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Revision History 221
Eco Plan
Orderable Device Status Package
MSL Peak Temp
Qty
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Important Notice
