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Texas Instruments warranty TMS320C6454 L1P Memory Configurations

Models: TMS320C6454

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TMS320C6454

Fixed-Point Digital Signal Processor

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SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

∙Region 1 size is 32K bytes with no wait states.

L1D is a two-way set-associative cache while L1P is a direct-mapped cache.

The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C64x+ Megamodule. After device reset, L1P and L1D cache are configured as all cache or all SRAM. The on-chip Bootloader changes the reset configuration for L1P and L1D. For more information, see the TMS320C645x Bootloader User's Guide (literature number SPRUEC6).

Figure 5-2and Figure 5-3show the available SRAM/cache configurations for L1P and L1D, respectively.

PRODUCT

000

All

SRAM

L1P mode bits

001 010 011

1/2

SRAM

	3/4
7/8	SRAM

SRAM

				direct
				mapped
				mapped
		direct		cache
		direct
		mapped
dm		mapped
dm		cache
cache

100

direct mapped cache

L1P memory

16K bytes

8K bytes

4K bytes

4K bytes

Block base address

00E0 0000h

00E0 4000h

00E0 6000h

00E0 7000h

00E0 8000h

Figure 5-2. TMS320C6454 L1P Memory Configurations

PREVIEW

000

All

SRAM

L1D mode bits

001 010 011

1/2

SRAM

	3/4
7/8	SRAM

SRAM

2-way cache

		2-way
2-way		cache
cache

100

2-way cache

L1D memory

16K bytes

8K bytes

4K bytes

4K bytes

Block base address

00F0 0000h

00F0 4000h

00F0 6000h

00F0 7000h

00F0 8000h

Figure 5-3. TMS320C6454 L1D Memory Configurations

78

C64x+ Megamodule

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Texas Instruments warranty TMS320C6454 L1P Memory Configurations

Contents

TMS320C6454 Fixed-Point Digital Signal Processor Features1 ZTZ/GTZ BGA Package Bottom View DescriptionZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View Submit Documentation Feedback Functional Block Diagram Functional Block DiagramContents Temperature Unless Otherwise NotedHardware Features Device CharacteristicsCharacteristics of the C6454 Processor C6454Fixed-Point Digital Signal Processor CPU DSP Core DescriptionProduct Preview Preview Memory Map Summary C6454 Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range 3CFF Ffff 2FFF FfffFfff 4FFF FfffBoot Sequence Boot Modes Supported2 2nd-Level Bootloaders Pin Assignments Pin MapC6454 Pin Map Bottom View Quadrant B C6454 Pin Map Bottom View Quadrant C C6454 Pin Map Bottom View Quadrant D Signal Groups Description Gpio TOUTL0 TINPL0 TMS320C6454 Fixed-Point Digital Signal ProcessorTINPL1 TOUTL1 SYSCLK4/GP1AACE2A ACE5A ACE4AACE3A ABE7 ABE6 ABE5 ABE4CLKR1/GP0 HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 onlyHpia Clks SharedRgmdclk MdioRgmdio MdclkPCBE3 HHWIL/PCLKPidsel HR/W/PCBE2 PINTA/GP14 HDS2/PCBE1Terminal Functions Terminal FunctionsType 1 IPD/IPU NameEmifa 64-BIT Control Signals Common to ALL Types of Memory IPD/IPU Emifa 64-BIT BUS ArbitrationEmifa 64-BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control AEA15 Name Emifa 64-BIT AddressAEA1916 AEA14AEA6 Signal NameType 1 IPD/IPU 2DESCRIPTION AEA3Name Emifa 64-BIT Data IPD/IPU Description Name DDR2 Memory Controller 32-BIT Address Timer IPD/IPU Description Name DDR2 Memory Controller 32-BIT DataINTER-INTEGRATED Circuit I2C Management Data INPUT/OUTPUT Mdio for MII/RMII/GMII Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 Management Data INPUT/OUTPUT Mdio for RgmiiEthernet MAC Emac Rgmii Reserved for TestRSV14 RSV12RSV13 RSV15RSV19 RSV17RSV18 RSV20Supply Voltage Monitor Pins Supply Voltage PinsIPD/IPU Description E18 AA1 AA6 AB7AC6 AC9 AF1 AD5 AD7AE6 AE8 CV DDGround Pins GNDF20 F22 F24 G11 G13 G15 G17 G19 G21 G23 M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18 AA2 AA7 AB6AC7 AC8 AF2 AD6AE4 AE7 AH1Device Support DevelopmentDevelopment Support Device and Development-Support Tool NomenclatureDevice Family Temperature RangePrefix DeviceProduct Preview Configuration IPD PIN Device Configuration at Device ResetC6454 Device Configuration Pins AEA190, ABA10, and Pcien AEA15AEA8 AEA14AEA13 AEA6AEA6 PIN AEA8 PIN AEA14 PIN Peripheral Configuration at Device ResetPCI Lower UpperPeripheral Selection After Device Reset MACSEL10 Peripheral Selection EmacPeripheral States Static Powerdown Reset Enable Progress Disabled Enabled Unlock the PERCFG0 register by Using the Perlock registerDevice State Control Registers Device State Control RegistersHEX Address Range Acronym Register Name Bit Field Value Description 310 Peripheral Lock Register DescriptionLockval LockvalPeripheral Configuration Register 0 Description Bit FieldDescription Mode control for I2C Peripheral Configuration Register 1 Description DDR2CTL EmifactlDDR2CTL Hpistat I2CSTAT Gpiostat TIMER1STAT TIMER0STAT EmacstatPeripheral Status Registers Description I2CSTAT1715 Pcistat Emac Configuration Register Emaccfg Description RmiirstEmulator Buffer Powerdown Register Emubufpd Description EmuctlSysclkout MCBSP1EN PCI66 Device Status Register DescriptionEmifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0 Pcieeai MACSEL1 MACSEL0MACSEL10 Bit Field Value DescriptionPcieeai LendianPullup/Pulldown Resistors BOOTMODE30Jtag ID Jtagid Register Description Variant Part Number Manufacturer LSBProduct Preview Configuration Examples Timers + Emac Gmii + Mdio Internal Buses, Bridges, and Switch Fabrics System InterconnectData Switch Fabric Connections Switched Central Resource Block Diagram TMS320C6454Configuration Switch Fabric SCR Connection MatrixC64x+ Megamodule SCR Connection Priority Allocation Host EmacSram Memory ArchitectureAET ROM aTMS320C6454 L1P Memory Configurations TMS320C6454 L2 Memory Configurations Available Memory Page Protection Schemes Memory ProtectionBandwidth Management AID0 BitMegamodule Reset Global or Local Power-Down ControlMegamodule Resets Reset Type MegamoduleVersion Megamodule RevisionVersion Revision a RevisionC64x+ Megamodule Register Descriptions Megamodule Interrupt RegistersMegamodule Powerdown Control Registers Megamodule Revision RegisterMegamodule Idma Registers Megamodule Cache Configuration Registers MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff Megamodule L1/L2 Memory Protection Registers L2MPPA5 L2MPPA3L2MPPA4 L2MPPA611. Device Configuration Registers Chip-Level Registers 10. CPU Megamodule Bandwidth Management RegistersHEX Address Range Acronym Register Name Comments Recommended Operating Conditions CvddRecommended Operating Conditions MIN NOM MAX UnitII DC Parameter Test Conditions MIN TYP MAX UnitOH = MAX TDO DVDD33 = MIN IOL = MAXTDO Parameter Information 1 3.3-V Signal Transition Levels2 3.3-V Signal Transition Rates Tester Pin ElectronicsTiming Parameters and Board Routing Analysis Power-Supply Sequencing Recommended Clock and Control Signal Transition BehaviorPower Supplies Power-Supply DecouplingProduct Preview Enhanced Direct Memory Access EDMA3 Controller EDMA3 Device-Specific InformationEDMA3 Channel Synchronization Events C6454 EDMA3 Channel Synchronization Events1Edma Binary Event Name Event Description Channel EDMA3 Peripheral Register Descriptions C6454 EDMA3 Channel Synchronization EventsEDMA3 Channel Controller Registers DCHMAP34 DCHMAP32DCHMAP33 DCHMAP35Emcr EMREmrh EmcrhQ1E0 Event Queue 1 Entry Register QSTAT2 QSTAT0QSTAT1 QSTAT3EDMA3 Parameter RAM1 EDMA3 Parameter RAM EDMA3 Transfer Controller 0 RegistersEDMA3 Transfer Controller 1 Registers EDMA3 Transfer Controller 2 Registers 109 EDMA3 Transfer Controller 3 Registers 111 10. C6454 DSP Interrupts InterruptsInterrupt Sources and Interrupt Controller Event Number Interrupt Event Interrupt SourceTINTLO1 TINTLO0TINTHI0 TINTHI1L2DMPA IdmacmpaIdmabuserr External Interrupts Electrical Data/Timing 11. Timing Requirements for External Interrupts1 see FigureNMI 12. Reset Types Reset ControllerPower-on Reset POR Pin Type InitiatorWarm Reset Reset Pin System Reset CPU ResetReset Priority Reset Controller RegisterReset Type Status Register Description 720 1000 Reset Electrical Data/Timing14. Timing Requirements for Reset1 2 3see -8and Figure ParameterPower-Up Timing TMS320C6454Resetstat CLKIN1 CLKIN2 PORPLL1 and PLL1 Controller 1 PLL1 Controller Device-Specific Information Internal Clocks and Maximum Operating Frequencies16. PLL1 Clock Frequency Ranges 1.3 PLL1 Stabilization, Lock, and Reset TimesClock Signal MIN MAX Unit 1.2 PLL1 Controller Operating Modes2 PLL1 Controller Memory Map 17. PLL1 Stabilization, Lock, and Reset Times18. PLL1 Controller Registers Including Reset Controller MIN TYPPllrst 3 PLL1 Controller Register Descriptions3.1 PLL1 Control Register PllpwrdnPLL Multiplier Control Register 20. PLL Multiplier Control Register Pllm Field DescriptionsPLL Pre-Divider Control Register PredenRatio PLL Controller Divider 4 Register D4ENPLL Controller Divider 5 Register D5ENPLL Controller Command Register GosetPLL Controller Status Register GostatPLL Controller Clock Align Control Register Plldiv Ratio Change Status Register SYS5 SYS4SYS5 Sysclk Status Register SYS5ON SYS4ON SYS3ON SYS2ONPLL Modes Unit 29. Timing Requirements for CLKIN1 Devices1 2 3 see Figure720 850 1000 X1 Bypass X20, x25, x30PLL2 and PLL2 Controller 1.2 PLL2 Controller Operating Modes 1 PLL2 Controller Device-Specific Information31. PLL2 Clock Frequency Ranges Pllref Pllen =32. PLL2 Controller Registers 2 PLL2 Controller Memory Map3 PLL2 Controller Register Descriptions HEX Address Range Acronym DescriptionPLL Controller Divider 1 Register D1ENPLL Controller Command Register ALN1 SYS1 SYS1ON 4 PLL2 Controller Input Clock Electrical Data/Timing 39. Timing Requirements for CLKIN21 2 3 see FigureDDR2 Memory Controller 1 DDR2 Memory Controller Device-Specific Information2 DDR2 Memory Controller Peripheral Register Descriptions 3 DDR2 Memory Controller Electrical Data/Timing40. DDR2 Memory Controller Registers External Memory Interface a Emifa Emifa Device-Specific InformationEmifa Peripheral Register Descriptions 41. Emifa RegistersEmifa Electrical Data/Timing 42. Timing Requirements for Aeclkin for EMIFA1 2 see FigureAeclkin 720 Aeclkin AECLKOUT1720 850 1000UNIT ABA10 AED630 Read Data Setup = Hold =ACEx ABE70 AAOE/ASOE a AAWE/ASWE a AR/W Aardy B DeassertedStrobe Setup = Extended Strobe ABA10 AED630Aeclkout Aardya Asserted Deasserted 155 EA1 EA2 EA3 EA4 BE1 BE2 BE3 BE4AEA190/ABA10 ASADS/ASREB AAOE/ASOEB AAWE/ASWEBWrite Latency = DSP Owns Bus HOLD/HOLDA TimingHHOLDAL-HOLDL Hold time, Hold low after Holda low Hold HoldaDelay time, Aeclkout high to Abusreq valid AECLKOUTx Busreq Timing11 I2C Peripheral 11.1 I2C Device-Specific InformationI2CCLKH I2CSAR I2COARSCL I2CXSR11.2 I2C Peripheral Register Descriptions 51. I2C RegistersStandard Mode Fast Mode MIN MAX 11.3 I2C Electrical Data/TimingSDA SCL Stop Start RepeatedUnit MAX Stop Start Start StopHPI Peripheral Register Descriptions Host-Port Interface HPI PeripheralHPI Device-Specific Information 54. HPI Control RegistersHPI Electrical Data/Timing See -56through Figure HR/W Hhwil Hstrobea HCS HasHCNTL10 HD150HR/W Hhwil Hstrobe a Hrdyb46. HPI16 Write Timing has Not Used, Tied High 47. HPI16 Write Timing has Used Has input HCNTL10 input HR/W input HCS input HD310 output Hrdyb output49. HPI32 Read Timing has Used 50. HPI32 Write Timing has Not Used, Tied High Input HCS input51. HPI32 Write Timing has Used Input HCS input HD310 inputMultichannel Buffered Serial Port McBSP McBSP Device-Specific Information 58. McBSP 1 Registers McBSP Electrical Data/Timing Product181 Clks Clkr ClkxClks Master Slave MIN MAX Slave MIN MAXClkx FSX Master Slave MIN Setup time, DR valid before Clkx high 18P Hold time, DR valid after Clkx high + 36P186 Ethernet MAC Emac Ethernet BusEmac Device-Specific Information Interface Modes70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii Modes Ball Number Device PIN NameRmii Interface Mode Clocking Emac Peripheral Register Descriptions 71. Ethernet MAC Emac Control RegistersRX5FREEBUFFER MacconfigSoftreset RX6FREEBUFFER72. Emac Statistics Registers HEX Address Range Acronym73. Emac Control Module Registers 74. Emac Descriptor Memory02C8 2000 02C8 3FFF Emac Descriptor Memory Emac Electrical Data/Timing MtclkMrclk Input MRXD7−MRXD4GMII only Output 720 1000UNIT 1000 Mbps1000 Mbps 100/10 Mbps MRXD3−MRXD0MTXD3−MTXD0 NO.PARAMETERMTXD7−MTXD0 Emac Rmii Electrical Data/Timing RmrefclkRmrefclk Input MRXD1-MRXD0 McrsdvMrxer Inputs 720 1000 Emac Rgmii Electrical Data/Timing Output201 70. Emac Transmit Interface Timing Rgmii OperationAB Management Data Input/Output Mdio Mdio Device-Specific InformationMdio Peripheral Register Descriptions 89. Mdio Registers Delay time, Mdclk low to Mdio data output valid 100 Mdio inputMdio output Timers Peripheral Register Descriptions TimersTimers Device-Specific Information 92. Timer 0 RegistersTimers Electrical Data/Timing 94. Timing Requirements for Timer Inputs1 see FigureTINPLx TOUTLx Peripheral Component Interconnect PCI 96. Default Values for PCI Configuration RegistersRegister Default Value PCI Device-Specific Information97. PCI Configuration Registers PCI Peripheral Register Descriptions98. PCI Back End Configuration Registers 99. DSP-toPCI Address Translation Registers 100. PCI Hook Configuration Registers 101. PCI External Memory SpaceHEX Address Offset Acronym Register Name 49FF Ffff 47FF Ffff48FF Ffff 4A7F FfffPCI Electrical Data/Timing Gpio Peripheral Register Descriptions General-Purpose Input/Output GpioGpio Device-Specific Information 102. Gpio RegistersGpio Electrical Data/Timing 103. Timing Requirements for Gpio Inputs1 2 see FigureGPIx GPOx Ieee 1149.1 Jtag Compatibility Statement Ieee 1149.1 JtagJtag Device-Specific Information 105. Timing Requirements for Jtag Test Port see FigurePackaging Information Thermal Resistance Characteristics S-PBGA Package ZTZ/GTZThermal Data AIR FlowRevision History C6454 Revision HistorySee ADDITIONS/MODIFICATIONS/DELETIONS Changed -4title to EDMA3 Channel Controller Registers Product Preview Revision History 221 MSL Peak Temp Orderable Device Status PackageEco Plan QtyPage Page Important Notice