PLL Pre-Divider Control Register | Texas Instruments TMS320C6454

TMS320C6454

Fixed-Point Digital Signal Processor

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SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

7.7.3.3 PLL Pre-Divider Control Register

The PLL pre-divider control register (PREDIV) is shown in Figure 7-13and described in Table 7-21.

31					16
			Reserved
			R-0
15	14		5	4	0
PREDEN			Reserved		RATIO
R/W-1			R-0		R/W-2h
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset
	Figure 7-13. PLL Pre-Divider Control Register (PREDIV) [Hex Address: 029A 0114]
		Table 7-21. PLL Pre-Divider Control Register (PREDIV) Field Descriptions
Bit	Field	Value	Description
31:16	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
15	PREDEN		Pre-divider enable bit.
		0	Pre-divider is disabled. No clock output.
		1	Pre-divider is enabled.
14:5	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
4:0	RATIO	0-1Fh	Divider ratio bits.
		0	÷1. Divide frequency by 1.
		1h	÷2. Divide frequency by 2.
		2h	÷3. Divide frequency by 3.
		3h-1Fh	Reserved, do not use.

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C64x+ Peripheral Information and Electrical Specifications

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Texas Instruments TMS320C6454 warranty PLL Pre-Divider Control Register, Preden, Ratio

Contents

Features TMS320C6454 Fixed-Point Digital Signal Processor 1 ZTZ/GTZ BGA Package Bottom View DescriptionZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View Submit Documentation Feedback Functional Block Diagram Functional Block Diagram Temperature Unless Otherwise Noted Contents Characteristics of the C6454 Processor Device CharacteristicsHardware Features C6454 CPU DSP Core Description Fixed-Point Digital Signal Processor Product Preview Preview Memory Map Summary C6454 Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range Ffff 2FFF Ffff3CFF Ffff 4FFF Ffff Boot Modes Supported Boot Sequence 2 2nd-Level Bootloaders Pin Map Pin Assignments C6454 Pin Map Bottom View Quadrant B C6454 Pin Map Bottom View Quadrant C C6454 Pin Map Bottom View Quadrant D Signal Groups Description TINPL1 TOUTL1 TMS320C6454 Fixed-Point Digital Signal ProcessorGpio TOUTL0 TINPL0 SYSCLK4/GP1A ACE3A ACE5A ACE4AACE2A ABE7 ABE6 ABE5 ABE4 Hpia HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 onlyCLKR1/GP0 Clks Shared Rgmdio MdioRgmdclk Mdclk Pidsel HHWIL/PCLKPCBE3 HR/W/PCBE2 PINTA/GP14 HDS2/PCBE1 Terminal Functions Terminal Functions Name Type 1 IPD/IPU Emifa 64-BIT Control Signals Common to ALL Types of Memory IPD/IPU Emifa 64-BIT BUS ArbitrationEmifa 64-BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control AEA1916 Name Emifa 64-BIT AddressAEA15 AEA14 Type 1 IPD/IPU 2DESCRIPTION Signal NameAEA6 AEA3 Name Emifa 64-BIT Data IPD/IPU Description Name DDR2 Memory Controller 32-BIT Address Timer IPD/IPU Description Name DDR2 Memory Controller 32-BIT DataINTER-INTEGRATED Circuit I2C Multichannel Buffered Serial Port 0 McBSP0 Multichannel Buffered Serial Port 1 McBSP1Management Data INPUT/OUTPUT Mdio for MII/RMII/GMII Management Data INPUT/OUTPUT Mdio for Rgmii Reserved for Test Ethernet MAC Emac Rgmii RSV13 RSV12RSV14 RSV15 RSV18 RSV17RSV19 RSV20 Supply Voltage Monitor Pins Supply Voltage PinsIPD/IPU Description E18 AA1 AA6 AB7AC6 AC9 AE6 AE8 AD5 AD7AF1 CV DD GND Ground Pins F20 F22 F24 G11 G13 G15 G17 G19 G21 G23 M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18 AA2 AA7 AB6AC7 AC8 AE4 AE7 AD6AF2 AH1 Development Support DevelopmentDevice Support Device and Development-Support Tool Nomenclature Prefix Temperature RangeDevice Family Device Product Preview C6454 Device Configuration Pins AEA190, ABA10, and Pcien Device Configuration at Device ResetConfiguration IPD PIN AEA15 AEA13 AEA14AEA8 AEA6 PCI Peripheral Configuration at Device ResetAEA6 PIN AEA8 PIN AEA14 PIN Lower Upper Peripheral Selection After Device Reset MACSEL10 Peripheral Selection EmacPeripheral States Unlock the PERCFG0 register by Using the Perlock register Static Powerdown Reset Enable Progress Disabled Enabled Device State Control Registers Device State Control RegistersHEX Address Range Acronym Register Name Lockval Peripheral Lock Register DescriptionBit Field Value Description 310 Lockval Peripheral Configuration Register 0 Description Bit FieldDescription Mode control for I2C Peripheral Configuration Register 1 Description DDR2CTL EmifactlDDR2CTL Peripheral Status Registers Description I2CSTAT Gpiostat TIMER1STAT TIMER0STAT EmacstatHpistat I2CSTAT 1715 Pcistat Rmiirst Emac Configuration Register Emaccfg Description Emuctl Emulator Buffer Powerdown Register Emubufpd Description Emifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0 Device Status Register DescriptionSysclkout MCBSP1EN PCI66 Pcieeai MACSEL1 MACSEL0 Pcieeai Bit Field Value DescriptionMACSEL10 Lendian Jtag ID Jtagid Register Description BOOTMODE30Pullup/Pulldown Resistors Variant Part Number Manufacturer LSB Product Preview Configuration Examples Timers + Emac Gmii + Mdio System Interconnect Internal Buses, Bridges, and Switch Fabrics Data Switch Fabric Connections TMS320C6454 Switched Central Resource Block Diagram SCR Connection Matrix Configuration Switch Fabric C64x+ Megamodule SCR Connection Host Emac Priority Allocation AET Memory ArchitectureSram ROM a TMS320C6454 L1P Memory Configurations TMS320C6454 L2 Memory Configurations Bandwidth Management Memory ProtectionAvailable Memory Page Protection Schemes AID0 Bit Megamodule Resets Power-Down ControlMegamodule Reset Global or Local Reset Type Megamodule Version Revision a Megamodule RevisionVersion Revision Megamodule Interrupt Registers C64x+ Megamodule Register Descriptions Megamodule Powerdown Control Registers Megamodule Revision RegisterMegamodule Idma Registers Megamodule Cache Configuration Registers MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff Megamodule L1/L2 Memory Protection Registers L2MPPA4 L2MPPA3L2MPPA5 L2MPPA6 11. Device Configuration Registers Chip-Level Registers 10. CPU Megamodule Bandwidth Management RegistersHEX Address Range Acronym Register Name Comments Cvdd Recommended Operating Conditions MIN NOM MAX Unit Recommended Operating Conditions OH = MAX Parameter Test Conditions MIN TYP MAX UnitII DC TDO DVDD33 = MIN IOL = MAX TDO 2 3.3-V Signal Transition Rates 1 3.3-V Signal Transition LevelsParameter Information Tester Pin Electronics Timing Parameters and Board Routing Analysis Power Supplies Recommended Clock and Control Signal Transition BehaviorPower-Supply Sequencing Power-Supply Decoupling Product Preview EDMA3 Device-Specific Information Enhanced Direct Memory Access EDMA3 Controller EDMA3 Channel Synchronization Events C6454 EDMA3 Channel Synchronization Events1Edma Binary Event Name Event Description Channel EDMA3 Peripheral Register Descriptions C6454 EDMA3 Channel Synchronization EventsEDMA3 Channel Controller Registers DCHMAP33 DCHMAP32DCHMAP34 DCHMAP35 Emrh EMREmcr Emcrh Q1E0 Event Queue 1 Entry Register QSTAT1 QSTAT0QSTAT2 QSTAT3 EDMA3 Parameter RAM1 EDMA3 Transfer Controller 0 Registers EDMA3 Parameter RAM EDMA3 Transfer Controller 1 Registers EDMA3 Transfer Controller 2 Registers 109 EDMA3 Transfer Controller 3 Registers 111 Interrupt Sources and Interrupt Controller Interrupts10. C6454 DSP Interrupts Event Number Interrupt Event Interrupt Source TINTHI0 TINTLO0TINTLO1 TINTHI1 L2DMPA IdmacmpaIdmabuserr External Interrupts Electrical Data/Timing 11. Timing Requirements for External Interrupts1 see FigureNMI Power-on Reset POR Pin Reset Controller12. Reset Types Type Initiator Warm Reset Reset Pin CPU Reset System Reset Reset Priority Reset Controller RegisterReset Type Status Register Description 14. Timing Requirements for Reset1 2 3see -8and Figure Reset Electrical Data/Timing720 1000 Parameter TMS320C6454 Power-Up Timing CLKIN1 CLKIN2 POR Resetstat PLL1 and PLL1 Controller Internal Clocks and Maximum Operating Frequencies 1 PLL1 Controller Device-Specific Information Clock Signal MIN MAX Unit 1.3 PLL1 Stabilization, Lock, and Reset Times16. PLL1 Clock Frequency Ranges 1.2 PLL1 Controller Operating Modes 18. PLL1 Controller Registers Including Reset Controller 17. PLL1 Stabilization, Lock, and Reset Times2 PLL1 Controller Memory Map MIN TYP 3.1 PLL1 Control Register 3 PLL1 Controller Register DescriptionsPllrst Pllpwrdn 20. PLL Multiplier Control Register Pllm Field Descriptions PLL Multiplier Control Register PLL Pre-Divider Control Register PredenRatio D4EN PLL Controller Divider 4 Register D5EN PLL Controller Divider 5 Register Goset PLL Controller Command Register Gostat PLL Controller Status Register PLL Controller Clock Align Control Register Plldiv Ratio Change Status Register SYS5 SYS4SYS5 SYS5ON SYS4ON SYS3ON SYS2ON Sysclk Status Register 720 850 1000 29. Timing Requirements for CLKIN1 Devices1 2 3 see FigurePLL Modes Unit X1 Bypass X20, x25, x30 PLL2 and PLL2 Controller 31. PLL2 Clock Frequency Ranges 1 PLL2 Controller Device-Specific Information1.2 PLL2 Controller Operating Modes Pllref Pllen = 3 PLL2 Controller Register Descriptions 2 PLL2 Controller Memory Map32. PLL2 Controller Registers HEX Address Range Acronym Description D1EN PLL Controller Divider 1 Register PLL Controller Command Register ALN1 SYS1 SYS1ON 39. Timing Requirements for CLKIN21 2 3 see Figure 4 PLL2 Controller Input Clock Electrical Data/Timing 1 DDR2 Memory Controller Device-Specific Information DDR2 Memory Controller 2 DDR2 Memory Controller Peripheral Register Descriptions 3 DDR2 Memory Controller Electrical Data/Timing40. DDR2 Memory Controller Registers Emifa Device-Specific Information External Memory Interface a Emifa 41. Emifa Registers Emifa Peripheral Register Descriptions Emifa Electrical Data/Timing 42. Timing Requirements for Aeclkin for EMIFA1 2 see FigureAeclkin 720 Aeclkin AECLKOUT1720 850 1000UNIT ACEx ABE70 Setup = Hold =ABA10 AED630 Read Data AAOE/ASOE a AAWE/ASWE a AR/W Aardy B Deasserted Strobe Setup = Extended Strobe ABA10 AED630Aeclkout Aardya Asserted Deasserted 155 AEA190/ABA10 BE1 BE2 BE3 BE4EA1 EA2 EA3 EA4 ASADS/ASREB AAOE/ASOEB AAWE/ASWEB Write Latency = HHOLDAL-HOLDL Hold time, Hold low after Holda low HOLD/HOLDA TimingDSP Owns Bus Hold Holda Busreq Timing Delay time, Aeclkout high to Abusreq valid AECLKOUTx 11.1 I2C Device-Specific Information 11 I2C Peripheral SCL I2COARI2CCLKH I2CSAR I2CXSR 51. I2C Registers 11.2 I2C Peripheral Register Descriptions 11.3 I2C Electrical Data/Timing Standard Mode Fast Mode MIN MAX SDA SCL Stop Start RepeatedUnit MAX Start Stop Stop Start HPI Device-Specific Information Host-Port Interface HPI PeripheralHPI Peripheral Register Descriptions 54. HPI Control Registers HPI Electrical Data/Timing See -56through Figure HCNTL10 HCS HasHR/W Hhwil Hstrobea HD150 Hrdyb HR/W Hhwil Hstrobe a 46. HPI16 Write Timing has Not Used, Tied High 47. HPI16 Write Timing has Used HCS input HD310 output Hrdyb output Has input HCNTL10 input HR/W input 49. HPI32 Read Timing has Used Input HCS input 50. HPI32 Write Timing has Not Used, Tied High Input HCS input HD310 input 51. HPI32 Write Timing has Used Multichannel Buffered Serial Port McBSP McBSP Device-Specific Information 58. McBSP 1 Registers Product McBSP Electrical Data/Timing 181 Clks Clkr ClkxClks Master Slave MIN MAX Slave MIN MAXClkx FSX Master Slave MIN Hold time, DR valid after Clkx high + 36P Setup time, DR valid before Clkx high 18P 186 Ethernet Bus Ethernet MAC Emac Interface Modes Emac Device-Specific Information 70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii Modes Ball Number Device PIN NameRmii Interface Mode Clocking 71. Ethernet MAC Emac Control Registers Emac Peripheral Register Descriptions Softreset MacconfigRX5FREEBUFFER RX6FREEBUFFER HEX Address Range Acronym 72. Emac Statistics Registers 73. Emac Control Module Registers 74. Emac Descriptor Memory02C8 2000 02C8 3FFF Emac Descriptor Memory Mtclk Emac Electrical Data/Timing 1000 Mbps 100/10 Mbps Output 720 1000UNIT 1000 MbpsMrclk Input MRXD7−MRXD4GMII only MRXD3−MRXD0 MTXD3−MTXD0 NO.PARAMETERMTXD7−MTXD0 Rmrefclk Emac Rmii Electrical Data/Timing Rmrefclk Input MRXD1-MRXD0 McrsdvMrxer Inputs 720 1000 Output Emac Rgmii Electrical Data/Timing 201 70. Emac Transmit Interface Timing Rgmii OperationAB Management Data Input/Output Mdio Mdio Device-Specific InformationMdio Peripheral Register Descriptions 89. Mdio Registers Delay time, Mdclk low to Mdio data output valid 100 Mdio inputMdio output Timers Device-Specific Information TimersTimers Peripheral Register Descriptions 92. Timer 0 Registers Timers Electrical Data/Timing 94. Timing Requirements for Timer Inputs1 see FigureTINPLx TOUTLx Register Default Value 96. Default Values for PCI Configuration RegistersPeripheral Component Interconnect PCI PCI Device-Specific Information PCI Peripheral Register Descriptions 97. PCI Configuration Registers 98. PCI Back End Configuration Registers 99. DSP-toPCI Address Translation Registers 100. PCI Hook Configuration Registers 101. PCI External Memory SpaceHEX Address Offset Acronym Register Name 48FF Ffff 47FF Ffff49FF Ffff 4A7F Ffff PCI Electrical Data/Timing Gpio Device-Specific Information General-Purpose Input/Output GpioGpio Peripheral Register Descriptions 102. Gpio Registers Gpio Electrical Data/Timing 103. Timing Requirements for Gpio Inputs1 2 see FigureGPIx GPOx Jtag Device-Specific Information Ieee 1149.1 JtagIeee 1149.1 Jtag Compatibility Statement 105. Timing Requirements for Jtag Test Port see Figure Thermal Data Thermal Resistance Characteristics S-PBGA Package ZTZ/GTZPackaging Information AIR Flow Revision History C6454 Revision HistorySee ADDITIONS/MODIFICATIONS/DELETIONS Changed -4title to EDMA3 Channel Controller Registers Product Preview Revision History 221 Eco Plan Orderable Device Status PackageMSL Peak Temp QtyPage Page Important Notice