ACE5A ACE4A, ACE3A, ACE2A, DCE0 | Texas Instruments TMS320C6454

PRODUCT PREVIEW

TMS320C6454

Fixed-Point Digital Signal Processor

	SPRS311A –APRIL 2006 –REVISED DECEMBER 2006
	64	Data
	AED[63:0]	Data
	ACE5(A)
	ACE4(A)	Memory Map
	ACE3(A)	Space Select
	ACE2(A)		External
			External
	20		Memory I/F
	20	Address	Control
	AEA[19:0]		Control
	AEA[19:0]
	ABE7
	ABE6
	ABE5
	ABE4	Byte Enables
	ABE3	Byte Enables
	ABE3
	ABE2
	ABE1
	ABE0
			Bus
			Arbitration
	ABA[1:0]	Bank Address
			EMIFA (64-bit Data Bus)
	32	Data
	DED[31:0]	Data

					Memory Map
	DCE0				Memory Map
	DCE0				Space Select	External
					Space Select

			14			Memory I/F
						Memory I/F
DEA[13:0]					Address	Control
						Control

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AECLKIN

AECLKOUT

ASWE/AAWE

AARDY

AR/W

AAOE/ASOE

ASADS/ASRE

AHOLD

AHOLDA

ABUSREQ

DDR2CLKOUT

DDR2CLKOUT

DSDCKE

DSDCAS

DSDRAS

DSDWE

DSDDQS[3:0]

DSDDQS[3:0]

DSDDQGATE[0]

DSDDQGATE[1]

DSDDQM3

DSDDQM2

DSDDQM1

DSDDQM0

Byte Enables

Bank Address

DSDDQGATE[2]

DSDDQGATE[3]

DEODT[1:0]

DBA[2:0]

DDR2 Memoty Controller (32-bit Data Bus)

A. The EMIFA ACE0 and ACE1 are not functionally supported on the C6454 device.

Figure 2-8. EMIFA/DDR2 Memory Controller Peripheral Signals

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Device Overview

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Image 20

Texas Instruments TMS320C6454 warranty ACE5A ACE4A, ACE3A, ACE2A, ABE7 ABE6 ABE5 ABE4, ABE3 ABE2 ABE1 ABE0, DCE0

Contents

TMS320C6454 Fixed-Point Digital Signal Processor Features ZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View 1 ZTZ/GTZ BGA Package Bottom ViewDescription Submit Documentation Feedback Functional Block Diagram Functional Block Diagram Contents Temperature Unless Otherwise Noted Device Characteristics Characteristics of the C6454 ProcessorHardware Features C6454 Fixed-Point Digital Signal Processor CPU DSP Core Description Product Preview Preview Memory Block Description Block Size Bytes HEX Address Range Memory Map SummaryC6454 Memory Map Summary 2FFF Ffff Ffff3CFF Ffff 4FFF Ffff Boot Sequence Boot Modes Supported 2 2nd-Level Bootloaders Pin Assignments Pin Map C6454 Pin Map Bottom View Quadrant B C6454 Pin Map Bottom View Quadrant C C6454 Pin Map Bottom View Quadrant D Signal Groups Description TMS320C6454 Fixed-Point Digital Signal Processor TINPL1 TOUTL1Gpio TOUTL0 TINPL0 SYSCLK4/GP1A ACE5A ACE4A ACE3AACE2A ABE7 ABE6 ABE5 ABE4 HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 only HpiaCLKR1/GP0 Clks Shared Mdio RgmdioRgmdclk Mdclk HHWIL/PCLK PidselPCBE3 HR/W/PCBE2 PINTA/GP14 HDS2/PCBE1 Terminal Functions Terminal Functions Type 1 IPD/IPU Name Emifa 64-BIT Control Signals Common to ALL Types of Memory Emifa 64-BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control IPD/IPUEmifa 64-BIT BUS Arbitration Name Emifa 64-BIT Address AEA1916AEA15 AEA14 Signal Name Type 1 IPD/IPU 2DESCRIPTIONAEA6 AEA3 Name Emifa 64-BIT Data IPD/IPU Description Name DDR2 Memory Controller 32-BIT Address INTER-INTEGRATED Circuit I2C TimerIPD/IPU Description Name DDR2 Memory Controller 32-BIT Data Multichannel Buffered Serial Port 1 McBSP1 Multichannel Buffered Serial Port 0 McBSP0Management Data INPUT/OUTPUT Mdio for MII/RMII/GMII Management Data INPUT/OUTPUT Mdio for Rgmii Ethernet MAC Emac Rgmii Reserved for Test RSV12 RSV13RSV14 RSV15 RSV17 RSV18RSV19 RSV20 IPD/IPU Description Supply Voltage Monitor PinsSupply Voltage Pins E18 AC6 AC9 AA1 AA6AB7 AD5 AD7 AE6 AE8AF1 CV DD Ground Pins GND F20 F22 F24 G11 G13 G15 G17 G19 G21 G23 M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18 AC7 AC8 AA2 AA7AB6 AD6 AE4 AE7AF2 AH1 Development Development SupportDevice Support Device and Development-Support Tool Nomenclature Temperature Range PrefixDevice Family Device Product Preview Device Configuration at Device Reset C6454 Device Configuration Pins AEA190, ABA10, and PcienConfiguration IPD PIN AEA15 AEA14 AEA13AEA8 AEA6 Peripheral Configuration at Device Reset PCIAEA6 PIN AEA8 PIN AEA14 PIN Lower Upper Peripheral States Peripheral Selection After Device ResetMACSEL10 Peripheral Selection Emac Static Powerdown Reset Enable Progress Disabled Enabled Unlock the PERCFG0 register by Using the Perlock register HEX Address Range Acronym Register Name Device State Control RegistersDevice State Control Registers Peripheral Lock Register Description LockvalBit Field Value Description 310 Lockval Description Peripheral Configuration Register 0 DescriptionBit Field Mode control for I2C DDR2CTL Peripheral Configuration Register 1 DescriptionDDR2CTL Emifactl I2CSTAT Gpiostat TIMER1STAT TIMER0STAT Emacstat Peripheral Status Registers DescriptionHpistat I2CSTAT 1715 Pcistat Emac Configuration Register Emaccfg Description Rmiirst Emulator Buffer Powerdown Register Emubufpd Description Emuctl Device Status Register Description Emifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0Sysclkout MCBSP1EN PCI66 Pcieeai MACSEL1 MACSEL0 Bit Field Value Description PcieeaiMACSEL10 Lendian BOOTMODE30 Jtag ID Jtagid Register DescriptionPullup/Pulldown Resistors Variant Part Number Manufacturer LSB Product Preview Configuration Examples Timers + Emac Gmii + Mdio Internal Buses, Bridges, and Switch Fabrics System Interconnect Data Switch Fabric Connections Switched Central Resource Block Diagram TMS320C6454 Configuration Switch Fabric SCR Connection Matrix C64x+ Megamodule SCR Connection Priority Allocation Host Emac Memory Architecture AETSram ROM a TMS320C6454 L1P Memory Configurations TMS320C6454 L2 Memory Configurations Memory Protection Bandwidth ManagementAvailable Memory Page Protection Schemes AID0 Bit Power-Down Control Megamodule ResetsMegamodule Reset Global or Local Reset Type Megamodule Megamodule Revision Version Revision aVersion Revision C64x+ Megamodule Register Descriptions Megamodule Interrupt Registers Megamodule Idma Registers Megamodule Powerdown Control RegistersMegamodule Revision Register Megamodule Cache Configuration Registers MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff Megamodule L1/L2 Memory Protection Registers L2MPPA3 L2MPPA4L2MPPA5 L2MPPA6 HEX Address Range Acronym Register Name Comments 11. Device Configuration Registers Chip-Level Registers10. CPU Megamodule Bandwidth Management Registers Recommended Operating Conditions Cvdd Recommended Operating Conditions MIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX Unit OH = MAXII DC TDO DVDD33 = MIN IOL = MAX TDO 1 3.3-V Signal Transition Levels 2 3.3-V Signal Transition RatesParameter Information Tester Pin Electronics Timing Parameters and Board Routing Analysis Recommended Clock and Control Signal Transition Behavior Power SuppliesPower-Supply Sequencing Power-Supply Decoupling Product Preview Enhanced Direct Memory Access EDMA3 Controller EDMA3 Device-Specific Information Edma Binary Event Name Event Description Channel EDMA3 Channel Synchronization EventsC6454 EDMA3 Channel Synchronization Events1 EDMA3 Channel Controller Registers EDMA3 Peripheral Register DescriptionsC6454 EDMA3 Channel Synchronization Events DCHMAP32 DCHMAP33DCHMAP34 DCHMAP35 EMR EmrhEmcr Emcrh Q1E0 Event Queue 1 Entry Register QSTAT0 QSTAT1QSTAT2 QSTAT3 EDMA3 Parameter RAM1 EDMA3 Parameter RAM EDMA3 Transfer Controller 0 Registers EDMA3 Transfer Controller 1 Registers EDMA3 Transfer Controller 2 Registers 109 EDMA3 Transfer Controller 3 Registers 111 Interrupts Interrupt Sources and Interrupt Controller10. C6454 DSP Interrupts Event Number Interrupt Event Interrupt Source TINTLO0 TINTHI0TINTLO1 TINTHI1 Idmabuserr L2DMPAIdmacmpa NMI External Interrupts Electrical Data/Timing11. Timing Requirements for External Interrupts1 see Figure Reset Controller Power-on Reset POR Pin12. Reset Types Type Initiator Warm Reset Reset Pin System Reset CPU Reset Reset Type Status Register Description Reset PriorityReset Controller Register Reset Electrical Data/Timing 14. Timing Requirements for Reset1 2 3see -8and Figure720 1000 Parameter Power-Up Timing TMS320C6454 Resetstat CLKIN1 CLKIN2 POR PLL1 and PLL1 Controller 1 PLL1 Controller Device-Specific Information Internal Clocks and Maximum Operating Frequencies 1.3 PLL1 Stabilization, Lock, and Reset Times Clock Signal MIN MAX Unit16. PLL1 Clock Frequency Ranges 1.2 PLL1 Controller Operating Modes 17. PLL1 Stabilization, Lock, and Reset Times 18. PLL1 Controller Registers Including Reset Controller2 PLL1 Controller Memory Map MIN TYP 3 PLL1 Controller Register Descriptions 3.1 PLL1 Control RegisterPllrst Pllpwrdn PLL Multiplier Control Register 20. PLL Multiplier Control Register Pllm Field Descriptions Ratio PLL Pre-Divider Control RegisterPreden PLL Controller Divider 4 Register D4EN PLL Controller Divider 5 Register D5EN PLL Controller Command Register Goset PLL Controller Status Register Gostat PLL Controller Clock Align Control Register SYS5 Plldiv Ratio Change Status RegisterSYS5 SYS4 Sysclk Status Register SYS5ON SYS4ON SYS3ON SYS2ON 29. Timing Requirements for CLKIN1 Devices1 2 3 see Figure 720 850 1000PLL Modes Unit X1 Bypass X20, x25, x30 PLL2 and PLL2 Controller 1 PLL2 Controller Device-Specific Information 31. PLL2 Clock Frequency Ranges1.2 PLL2 Controller Operating Modes Pllref Pllen = 2 PLL2 Controller Memory Map 3 PLL2 Controller Register Descriptions32. PLL2 Controller Registers HEX Address Range Acronym Description PLL Controller Divider 1 Register D1EN PLL Controller Command Register ALN1 SYS1 SYS1ON 4 PLL2 Controller Input Clock Electrical Data/Timing 39. Timing Requirements for CLKIN21 2 3 see Figure DDR2 Memory Controller 1 DDR2 Memory Controller Device-Specific Information 40. DDR2 Memory Controller Registers 2 DDR2 Memory Controller Peripheral Register Descriptions3 DDR2 Memory Controller Electrical Data/Timing External Memory Interface a Emifa Emifa Device-Specific Information Emifa Peripheral Register Descriptions 41. Emifa Registers Aeclkin Emifa Electrical Data/Timing42. Timing Requirements for Aeclkin for EMIFA1 2 see Figure 720 850 1000UNIT 720Aeclkin AECLKOUT1 Setup = Hold = ACEx ABE70ABA10 AED630 Read Data AAOE/ASOE a AAWE/ASWE a AR/W Aardy B Deasserted Aeclkout Aardya Asserted Deasserted Strobe Setup = Extended StrobeABA10 AED630 155 BE1 BE2 BE3 BE4 AEA190/ABA10EA1 EA2 EA3 EA4 ASADS/ASREB AAOE/ASOEB AAWE/ASWEB Write Latency = HOLD/HOLDA Timing HHOLDAL-HOLDL Hold time, Hold low after Holda lowDSP Owns Bus Hold Holda Delay time, Aeclkout high to Abusreq valid AECLKOUTx Busreq Timing 11 I2C Peripheral 11.1 I2C Device-Specific Information I2COAR SCLI2CCLKH I2CSAR I2CXSR 11.2 I2C Peripheral Register Descriptions 51. I2C Registers Standard Mode Fast Mode MIN MAX 11.3 I2C Electrical Data/Timing Unit MAX SDA SCLStop Start Repeated Stop Start Start Stop Host-Port Interface HPI Peripheral HPI Device-Specific InformationHPI Peripheral Register Descriptions 54. HPI Control Registers HPI Electrical Data/Timing See -56through Figure HCS Has HCNTL10HR/W Hhwil Hstrobea HD150 HR/W Hhwil Hstrobe a Hrdyb 46. HPI16 Write Timing has Not Used, Tied High 47. HPI16 Write Timing has Used Has input HCNTL10 input HR/W input HCS input HD310 output Hrdyb output 49. HPI32 Read Timing has Used 50. HPI32 Write Timing has Not Used, Tied High Input HCS input 51. HPI32 Write Timing has Used Input HCS input HD310 input Multichannel Buffered Serial Port McBSP McBSP Device-Specific Information 58. McBSP 1 Registers McBSP Electrical Data/Timing Product 181 Clks Clks ClkrClkx Clkx FSX Master Slave MIN MAXSlave MIN MAX Master Slave MIN Setup time, DR valid before Clkx high 18P Hold time, DR valid after Clkx high + 36P 186 Ethernet MAC Emac Ethernet Bus Emac Device-Specific Information Interface Modes Rmii 70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii ModesBall Number Device PIN Name Interface Mode Clocking Emac Peripheral Register Descriptions 71. Ethernet MAC Emac Control Registers Macconfig SoftresetRX5FREEBUFFER RX6FREEBUFFER 72. Emac Statistics Registers HEX Address Range Acronym 02C8 2000 02C8 3FFF Emac Descriptor Memory 73. Emac Control Module Registers74. Emac Descriptor Memory Emac Electrical Data/Timing Mtclk Output 720 1000UNIT 1000 Mbps 1000 Mbps 100/10 MbpsMrclk Input MRXD7−MRXD4GMII only MRXD3−MRXD0 MTXD7−MTXD0 MTXD3−MTXD0NO.PARAMETER Emac Rmii Electrical Data/Timing Rmrefclk Mrxer Inputs 720 1000 Rmrefclk InputMRXD1-MRXD0 Mcrsdv Emac Rgmii Electrical Data/Timing Output 201 70. Emac Transmit Interface Timing Rgmii OperationAB Mdio Peripheral Register Descriptions 89. Mdio Registers Management Data Input/Output MdioMdio Device-Specific Information Mdio output Delay time, Mdclk low to Mdio data output valid 100Mdio input Timers Timers Device-Specific InformationTimers Peripheral Register Descriptions 92. Timer 0 Registers TINPLx TOUTLx Timers Electrical Data/Timing94. Timing Requirements for Timer Inputs1 see Figure 96. Default Values for PCI Configuration Registers Register Default ValuePeripheral Component Interconnect PCI PCI Device-Specific Information 97. PCI Configuration Registers PCI Peripheral Register Descriptions 98. PCI Back End Configuration Registers 99. DSP-toPCI Address Translation Registers HEX Address Offset Acronym Register Name 100. PCI Hook Configuration Registers101. PCI External Memory Space 47FF Ffff 48FF Ffff49FF Ffff 4A7F Ffff PCI Electrical Data/Timing General-Purpose Input/Output Gpio Gpio Device-Specific InformationGpio Peripheral Register Descriptions 102. Gpio Registers GPIx GPOx Gpio Electrical Data/Timing103. Timing Requirements for Gpio Inputs1 2 see Figure Ieee 1149.1 Jtag Jtag Device-Specific InformationIeee 1149.1 Jtag Compatibility Statement 105. Timing Requirements for Jtag Test Port see Figure Thermal Resistance Characteristics S-PBGA Package ZTZ/GTZ Thermal DataPackaging Information AIR Flow See ADDITIONS/MODIFICATIONS/DELETIONS Revision HistoryC6454 Revision History Changed -4title to EDMA3 Channel Controller Registers Product Preview Revision History 221 Orderable Device Status Package Eco PlanMSL Peak Temp QtyPage Page Important Notice