Ipd/Ipu | Texas Instruments TMS320C6454 specification

TMS320C6454

Fixed-Point Digital Signal Processor

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SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

Table 2-3. Terminal Functions (continued)

	SIGNAL		TYPE (1)	IPD/IPU (2)
	NAME	NO.	TYPE (1)	IPD/IPU (2)
	NAME	NO.
	ACE5	V27	O/Z	IPU
	ACE4	V28	O/Z	IPU
	ACE3	W26	O/Z	IPU
	ACE2	W27	O/Z	IPU
	ABE7	W29	O/Z	IPU
	ABE6	K26	O/Z	IPU
	ABE5	L29	O/Z	IPU
	ABE4	L28	O/Z	IPU
	ABE3	AA29	O/Z	IPU
	ABE2	AA28	O/Z	IPU
	ABE1	AA25	O/Z	IPU
	ABE0	AA26	O/Z	IPU

DESCRIPTION

EMIFA memory space enables

∙ Enabled by bits 28 through 31 of the word address

∙ Only one pin is asserted during any external data access Note: The C6454 device does not have ACE0 and ACE1 pins

EMIFA byte-enable control

∙ Decoded from the low-order address bits. The number of address bits or byte enables used depends on the width of external memory.

∙ Byte-write enables for most types of memory.

				EMIFA (64-BIT) - BUS ARBITRATION
	AHOLDA	N26	O	IPU	EMIFA hold-request-acknowledge to the host
	AHOLD	R29	I	IPU	EMIFA hold request from the host
	ABUSREQ	L27	O	IPU	EMIFA bus request output
		EMIFA (64-BIT) - ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL
					EMIFA external input clock. The EMIFA input clock (AECLKIN or SYSCLK4
	AECLKIN	N29	I	IPD	clock) is selected at reset via the pullup/pulldown resistor on the AEA[15] pin.
					Note: AECLKIN is the default for the EMIFA input clock.
	AECLKOUT	V29	O/Z	IPD	EMIFA output clock [at EMIFA input clock (AECLKIN or SYSCLK4) frequency]
	AAWE/ASWE	AB25	O/Z	IPU	Asynchronous memory write-enable/Programmable synchronous interface
	AAWE/ASWE	AB25	O/Z	IPU	write-enable
					write-enable
	AARDY	K29	I	IPU	Asynchronous memory ready input
	AR/W	W25	O/Z	IPU	Asynchronous memory read/write
	AAOE/ASOE	Y28	O/Z	IPU	Asynchronous/Programmable synchronous memory output-enable
					Programmable synchronous address strobe or read-enable
					∙ For programmable synchronous interface, the r_enable field in the Chip
					Select x Configuration Register selects between ASADS and ASRE:
	ASADS/ASRE	R26	O/Z	IPU	– If r_enable = 0, then the ASADS/ASRE signal functions as the ASADS
					signal.

– If r_enable = 1, then the ASADS/ASRE signal functions as the ASRE signal.

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Texas Instruments TMS320C6454 Ipd/Ipu, Emifa 64-BIT BUS Arbitration, Emifa 64-BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control

Contents

Features TMS320C6454 Fixed-Point Digital Signal Processor 1 ZTZ/GTZ BGA Package Bottom View DescriptionZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View Submit Documentation Feedback Functional Block Diagram Functional Block Diagram Temperature Unless Otherwise Noted Contents C6454 Device CharacteristicsCharacteristics of the C6454 Processor Hardware Features CPU DSP Core Description Fixed-Point Digital Signal Processor Product Preview Preview Memory Map Summary C6454 Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range 4FFF Ffff 2FFF FfffFfff 3CFF Ffff Boot Modes Supported Boot Sequence 2 2nd-Level Bootloaders Pin Map Pin Assignments C6454 Pin Map Bottom View Quadrant B C6454 Pin Map Bottom View Quadrant C C6454 Pin Map Bottom View Quadrant D Signal Groups Description SYSCLK4/GP1A TMS320C6454 Fixed-Point Digital Signal ProcessorTINPL1 TOUTL1 Gpio TOUTL0 TINPL0 ABE7 ABE6 ABE5 ABE4 ACE5A ACE4AACE3A ACE2A Clks Shared HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 onlyHpia CLKR1/GP0 Mdclk MdioRgmdio Rgmdclk HR/W/PCBE2 PINTA/GP14 HDS2/PCBE1 HHWIL/PCLKPidsel PCBE3 Terminal Functions Terminal Functions Name Type 1 IPD/IPU Emifa 64-BIT Control Signals Common to ALL Types of Memory IPD/IPU Emifa 64-BIT BUS ArbitrationEmifa 64-BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control AEA14 Name Emifa 64-BIT AddressAEA1916 AEA15 AEA3 Signal NameType 1 IPD/IPU 2DESCRIPTION AEA6 Name Emifa 64-BIT Data IPD/IPU Description Name DDR2 Memory Controller 32-BIT Address Timer IPD/IPU Description Name DDR2 Memory Controller 32-BIT DataINTER-INTEGRATED Circuit I2C Management Data INPUT/OUTPUT Mdio for Rgmii Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 Management Data INPUT/OUTPUT Mdio for MII/RMII/GMII Reserved for Test Ethernet MAC Emac Rgmii RSV15 RSV12RSV13 RSV14 RSV20 RSV17RSV18 RSV19 Supply Voltage Monitor Pins Supply Voltage PinsIPD/IPU Description E18 AA1 AA6 AB7AC6 AC9 CV DD AD5 AD7AE6 AE8 AF1 GND Ground Pins F20 F22 F24 G11 G13 G15 G17 G19 G21 G23 M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18 AA2 AA7 AB6AC7 AC8 AH1 AD6AE4 AE7 AF2 Device and Development-Support Tool Nomenclature DevelopmentDevelopment Support Device Support Device Temperature RangePrefix Device Family Product Preview AEA15 Device Configuration at Device ResetC6454 Device Configuration Pins AEA190, ABA10, and Pcien Configuration IPD PIN AEA6 AEA14AEA13 AEA8 Lower Upper Peripheral Configuration at Device ResetPCI AEA6 PIN AEA8 PIN AEA14 PIN Peripheral Selection After Device Reset MACSEL10 Peripheral Selection EmacPeripheral States Unlock the PERCFG0 register by Using the Perlock register Static Powerdown Reset Enable Progress Disabled Enabled Device State Control Registers Device State Control RegistersHEX Address Range Acronym Register Name Lockval Peripheral Lock Register DescriptionLockval Bit Field Value Description 310 Peripheral Configuration Register 0 Description Bit FieldDescription Mode control for I2C Peripheral Configuration Register 1 Description DDR2CTL EmifactlDDR2CTL I2CSTAT I2CSTAT Gpiostat TIMER1STAT TIMER0STAT EmacstatPeripheral Status Registers Description Hpistat 1715 Pcistat Rmiirst Emac Configuration Register Emaccfg Description Emuctl Emulator Buffer Powerdown Register Emubufpd Description Pcieeai MACSEL1 MACSEL0 Device Status Register DescriptionEmifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0 Sysclkout MCBSP1EN PCI66 Lendian Bit Field Value DescriptionPcieeai MACSEL10 Variant Part Number Manufacturer LSB BOOTMODE30Jtag ID Jtagid Register Description Pullup/Pulldown Resistors Product Preview Configuration Examples Timers + Emac Gmii + Mdio System Interconnect Internal Buses, Bridges, and Switch Fabrics Data Switch Fabric Connections TMS320C6454 Switched Central Resource Block Diagram SCR Connection Matrix Configuration Switch Fabric C64x+ Megamodule SCR Connection Host Emac Priority Allocation ROM a Memory ArchitectureAET Sram TMS320C6454 L1P Memory Configurations TMS320C6454 L2 Memory Configurations AID0 Bit Memory ProtectionBandwidth Management Available Memory Page Protection Schemes Reset Type Megamodule Power-Down ControlMegamodule Resets Megamodule Reset Global or Local Revision Megamodule RevisionVersion Revision a Version Megamodule Interrupt Registers C64x+ Megamodule Register Descriptions Megamodule Powerdown Control Registers Megamodule Revision RegisterMegamodule Idma Registers Megamodule Cache Configuration Registers MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff Megamodule L1/L2 Memory Protection Registers L2MPPA6 L2MPPA3L2MPPA4 L2MPPA5 11. Device Configuration Registers Chip-Level Registers 10. CPU Megamodule Bandwidth Management RegistersHEX Address Range Acronym Register Name Comments Cvdd Recommended Operating Conditions MIN NOM MAX Unit Recommended Operating Conditions TDO DVDD33 = MIN IOL = MAX Parameter Test Conditions MIN TYP MAX UnitOH = MAX II DC TDO Tester Pin Electronics 1 3.3-V Signal Transition Levels2 3.3-V Signal Transition Rates Parameter Information Timing Parameters and Board Routing Analysis Power-Supply Decoupling Recommended Clock and Control Signal Transition BehaviorPower Supplies Power-Supply Sequencing Product Preview EDMA3 Device-Specific Information Enhanced Direct Memory Access EDMA3 Controller EDMA3 Channel Synchronization Events C6454 EDMA3 Channel Synchronization Events1Edma Binary Event Name Event Description Channel EDMA3 Peripheral Register Descriptions C6454 EDMA3 Channel Synchronization EventsEDMA3 Channel Controller Registers DCHMAP35 DCHMAP32DCHMAP33 DCHMAP34 Emcrh EMREmrh Emcr Q1E0 Event Queue 1 Entry Register QSTAT3 QSTAT0QSTAT1 QSTAT2 EDMA3 Parameter RAM1 EDMA3 Transfer Controller 0 Registers EDMA3 Parameter RAM EDMA3 Transfer Controller 1 Registers EDMA3 Transfer Controller 2 Registers 109 EDMA3 Transfer Controller 3 Registers 111 Event Number Interrupt Event Interrupt Source InterruptsInterrupt Sources and Interrupt Controller 10. C6454 DSP Interrupts TINTHI1 TINTLO0TINTHI0 TINTLO1 L2DMPA IdmacmpaIdmabuserr External Interrupts Electrical Data/Timing 11. Timing Requirements for External Interrupts1 see FigureNMI Type Initiator Reset ControllerPower-on Reset POR Pin 12. Reset Types Warm Reset Reset Pin CPU Reset System Reset Reset Priority Reset Controller RegisterReset Type Status Register Description Parameter Reset Electrical Data/Timing14. Timing Requirements for Reset1 2 3see -8and Figure 720 1000 TMS320C6454 Power-Up Timing CLKIN1 CLKIN2 POR Resetstat PLL1 and PLL1 Controller Internal Clocks and Maximum Operating Frequencies 1 PLL1 Controller Device-Specific Information 1.2 PLL1 Controller Operating Modes 1.3 PLL1 Stabilization, Lock, and Reset TimesClock Signal MIN MAX Unit 16. PLL1 Clock Frequency Ranges MIN TYP 17. PLL1 Stabilization, Lock, and Reset Times18. PLL1 Controller Registers Including Reset Controller 2 PLL1 Controller Memory Map Pllpwrdn 3 PLL1 Controller Register Descriptions3.1 PLL1 Control Register Pllrst 20. PLL Multiplier Control Register Pllm Field Descriptions PLL Multiplier Control Register PLL Pre-Divider Control Register PredenRatio D4EN PLL Controller Divider 4 Register D5EN PLL Controller Divider 5 Register Goset PLL Controller Command Register Gostat PLL Controller Status Register PLL Controller Clock Align Control Register Plldiv Ratio Change Status Register SYS5 SYS4SYS5 SYS5ON SYS4ON SYS3ON SYS2ON Sysclk Status Register X1 Bypass X20, x25, x30 29. Timing Requirements for CLKIN1 Devices1 2 3 see Figure720 850 1000 PLL Modes Unit PLL2 and PLL2 Controller Pllref Pllen = 1 PLL2 Controller Device-Specific Information31. PLL2 Clock Frequency Ranges 1.2 PLL2 Controller Operating Modes HEX Address Range Acronym Description 2 PLL2 Controller Memory Map3 PLL2 Controller Register Descriptions 32. PLL2 Controller Registers D1EN PLL Controller Divider 1 Register PLL Controller Command Register ALN1 SYS1 SYS1ON 39. Timing Requirements for CLKIN21 2 3 see Figure 4 PLL2 Controller Input Clock Electrical Data/Timing 1 DDR2 Memory Controller Device-Specific Information DDR2 Memory Controller 2 DDR2 Memory Controller Peripheral Register Descriptions 3 DDR2 Memory Controller Electrical Data/Timing40. DDR2 Memory Controller Registers Emifa Device-Specific Information External Memory Interface a Emifa 41. Emifa Registers Emifa Peripheral Register Descriptions Emifa Electrical Data/Timing 42. Timing Requirements for Aeclkin for EMIFA1 2 see FigureAeclkin 720 Aeclkin AECLKOUT1720 850 1000UNIT AAOE/ASOE a AAWE/ASWE a AR/W Aardy B Deasserted Setup = Hold =ACEx ABE70 ABA10 AED630 Read Data Strobe Setup = Extended Strobe ABA10 AED630Aeclkout Aardya Asserted Deasserted 155 ASADS/ASREB AAOE/ASOEB AAWE/ASWEB BE1 BE2 BE3 BE4AEA190/ABA10 EA1 EA2 EA3 EA4 Write Latency = Hold Holda HOLD/HOLDA TimingHHOLDAL-HOLDL Hold time, Hold low after Holda low DSP Owns Bus Busreq Timing Delay time, Aeclkout high to Abusreq valid AECLKOUTx 11.1 I2C Device-Specific Information 11 I2C Peripheral I2CXSR I2COARSCL I2CCLKH I2CSAR 51. I2C Registers 11.2 I2C Peripheral Register Descriptions 11.3 I2C Electrical Data/Timing Standard Mode Fast Mode MIN MAX SDA SCL Stop Start RepeatedUnit MAX Start Stop Stop Start 54. HPI Control Registers Host-Port Interface HPI PeripheralHPI Device-Specific Information HPI Peripheral Register Descriptions HPI Electrical Data/Timing See -56through Figure HD150 HCS HasHCNTL10 HR/W Hhwil Hstrobea Hrdyb HR/W Hhwil Hstrobe a 46. HPI16 Write Timing has Not Used, Tied High 47. HPI16 Write Timing has Used HCS input HD310 output Hrdyb output Has input HCNTL10 input HR/W input 49. HPI32 Read Timing has Used Input HCS input 50. HPI32 Write Timing has Not Used, Tied High Input HCS input HD310 input 51. HPI32 Write Timing has Used Multichannel Buffered Serial Port McBSP McBSP Device-Specific Information 58. McBSP 1 Registers Product McBSP Electrical Data/Timing 181 Clks Clkr ClkxClks Master Slave MIN MAX Slave MIN MAXClkx FSX Master Slave MIN Hold time, DR valid after Clkx high + 36P Setup time, DR valid before Clkx high 18P 186 Ethernet Bus Ethernet MAC Emac Interface Modes Emac Device-Specific Information 70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii Modes Ball Number Device PIN NameRmii Interface Mode Clocking 71. Ethernet MAC Emac Control Registers Emac Peripheral Register Descriptions RX6FREEBUFFER MacconfigSoftreset RX5FREEBUFFER HEX Address Range Acronym 72. Emac Statistics Registers 73. Emac Control Module Registers 74. Emac Descriptor Memory02C8 2000 02C8 3FFF Emac Descriptor Memory Mtclk Emac Electrical Data/Timing MRXD3−MRXD0 Output 720 1000UNIT 1000 Mbps1000 Mbps 100/10 Mbps Mrclk Input MRXD7−MRXD4GMII only MTXD3−MTXD0 NO.PARAMETERMTXD7−MTXD0 Rmrefclk Emac Rmii Electrical Data/Timing Rmrefclk Input MRXD1-MRXD0 McrsdvMrxer Inputs 720 1000 Output Emac Rgmii Electrical Data/Timing 201 70. Emac Transmit Interface Timing Rgmii OperationAB Management Data Input/Output Mdio Mdio Device-Specific InformationMdio Peripheral Register Descriptions 89. Mdio Registers Delay time, Mdclk low to Mdio data output valid 100 Mdio inputMdio output 92. Timer 0 Registers TimersTimers Device-Specific Information Timers Peripheral Register Descriptions Timers Electrical Data/Timing 94. Timing Requirements for Timer Inputs1 see FigureTINPLx TOUTLx PCI Device-Specific Information 96. Default Values for PCI Configuration RegistersRegister Default Value Peripheral Component Interconnect PCI PCI Peripheral Register Descriptions 97. PCI Configuration Registers 98. PCI Back End Configuration Registers 99. DSP-toPCI Address Translation Registers 100. PCI Hook Configuration Registers 101. PCI External Memory SpaceHEX Address Offset Acronym Register Name 4A7F Ffff 47FF Ffff48FF Ffff 49FF Ffff PCI Electrical Data/Timing 102. Gpio Registers General-Purpose Input/Output GpioGpio Device-Specific Information Gpio Peripheral Register Descriptions Gpio Electrical Data/Timing 103. Timing Requirements for Gpio Inputs1 2 see FigureGPIx GPOx 105. Timing Requirements for Jtag Test Port see Figure Ieee 1149.1 JtagJtag Device-Specific Information Ieee 1149.1 Jtag Compatibility Statement AIR Flow Thermal Resistance Characteristics S-PBGA Package ZTZ/GTZThermal Data Packaging Information Revision History C6454 Revision HistorySee ADDITIONS/MODIFICATIONS/DELETIONS Changed -4title to EDMA3 Channel Controller Registers Product Preview Revision History 221 Qty Orderable Device Status PackageEco Plan MSL Peak TempPage Page Important Notice