PLL Controller Divider 5 Register | Texas Instruments TMS320C6454

TMS320C6454

Fixed-Point Digital Signal Processor

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SPRS311A –APRIL 2006 –REVISED DECEMBER 2006

7.7.3.5 PLL Controller Divider 5 Register

The PLL controller divider 5 register (PLLDIV5) is shown in Figure 7-15and described in Table 7-23.

31				16
		Reserved
		R-0
15	14	5	4	0
D5EN	Reserved			RATIO
R/W-1	R-0			R/W-3

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Figure 7-15. PLL Controller Divider 5 Register (PLLDIV5) [Hex Address: 029A 0164]

Table 7-23. PLL Controller Divider 5 Register (PLLDIV5) Field Descriptions

Bit	Field	Value	Description
31:16	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
15	Dn4EN		Divider 4 enable bit.
		0	Divider 4 is disabled. No clock output.
		1	Divider 4 is enabled.
14:5	Reserved	0	Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
4:0	RATIO	0-1Fh	Divider ratio bits.
		0	÷1. Divide frequency by 1.
		1h	÷2. Divide frequency by 2.
		2h	÷3. Divide frequency by 3.
		3h	÷4. Divide frequency by 4.
		4h-7h	÷5 to ÷8. Divide frequency by 5 to divide frequency by 8.
		8h-1Fh	Reserved, do not use.

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C64x+ Peripheral Information and Electrical Specifications

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Texas Instruments TMS320C6454 warranty PLL Controller Divider 5 Register, D5EN

Contents

Features TMS320C6454 Fixed-Point Digital Signal Processor ZTZ/GTZ 697-PIN Ball Grid Array BGA Package Bottom View 1 ZTZ/GTZ BGA Package Bottom ViewDescription Submit Documentation Feedback Functional Block Diagram Functional Block Diagram Temperature Unless Otherwise Noted Contents C6454 Device CharacteristicsCharacteristics of the C6454 Processor Hardware Features CPU DSP Core Description Fixed-Point Digital Signal Processor Product Preview Preview Memory Block Description Block Size Bytes HEX Address Range Memory Map SummaryC6454 Memory Map Summary 4FFF Ffff 2FFF FfffFfff 3CFF Ffff Boot Modes Supported Boot Sequence 2 2nd-Level Bootloaders Pin Map Pin Assignments C6454 Pin Map Bottom View Quadrant B C6454 Pin Map Bottom View Quadrant C C6454 Pin Map Bottom View Quadrant D Signal Groups Description SYSCLK4/GP1A TMS320C6454 Fixed-Point Digital Signal ProcessorTINPL1 TOUTL1 Gpio TOUTL0 TINPL0 ABE7 ABE6 ABE5 ABE4 ACE5A ACE4AACE3A ACE2A Clks Shared HCNTL0/PSTOP HCNTL1/PDEVSEL HHWIL/PCLK HPI16 onlyHpia CLKR1/GP0 Mdclk MdioRgmdio Rgmdclk HR/W/PCBE2 PINTA/GP14 HDS2/PCBE1 HHWIL/PCLKPidsel PCBE3 Terminal Functions Terminal Functions Name Type 1 IPD/IPU Emifa 64-BIT Control Signals Common to ALL Types of Memory Emifa 64-BIT ASYNCHRONOUS/SYNCHRONOUS Memory Control IPD/IPUEmifa 64-BIT BUS Arbitration AEA14 Name Emifa 64-BIT AddressAEA1916 AEA15 AEA3 Signal NameType 1 IPD/IPU 2DESCRIPTION AEA6 Name Emifa 64-BIT Data IPD/IPU Description Name DDR2 Memory Controller 32-BIT Address INTER-INTEGRATED Circuit I2C TimerIPD/IPU Description Name DDR2 Memory Controller 32-BIT Data Management Data INPUT/OUTPUT Mdio for Rgmii Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 Management Data INPUT/OUTPUT Mdio for MII/RMII/GMII Reserved for Test Ethernet MAC Emac Rgmii RSV15 RSV12RSV13 RSV14 RSV20 RSV17RSV18 RSV19 IPD/IPU Description Supply Voltage Monitor PinsSupply Voltage Pins E18 AC6 AC9 AA1 AA6AB7 CV DD AD5 AD7AE6 AE8 AF1 GND Ground Pins F20 F22 F24 G11 G13 G15 G17 G19 G21 G23 M16 M18 M24 M26 M29 N13 N15 N17 N19 N23 P12 P14 P16 P18 AC7 AC8 AA2 AA7AB6 AH1 AD6AE4 AE7 AF2 Device and Development-Support Tool Nomenclature DevelopmentDevelopment Support Device Support Device Temperature RangePrefix Device Family Product Preview AEA15 Device Configuration at Device ResetC6454 Device Configuration Pins AEA190, ABA10, and Pcien Configuration IPD PIN AEA6 AEA14AEA13 AEA8 Lower Upper Peripheral Configuration at Device ResetPCI AEA6 PIN AEA8 PIN AEA14 PIN Peripheral States Peripheral Selection After Device ResetMACSEL10 Peripheral Selection Emac Unlock the PERCFG0 register by Using the Perlock register Static Powerdown Reset Enable Progress Disabled Enabled HEX Address Range Acronym Register Name Device State Control RegistersDevice State Control Registers Lockval Peripheral Lock Register DescriptionLockval Bit Field Value Description 310 Description Peripheral Configuration Register 0 DescriptionBit Field Mode control for I2C DDR2CTL Peripheral Configuration Register 1 DescriptionDDR2CTL Emifactl I2CSTAT I2CSTAT Gpiostat TIMER1STAT TIMER0STAT EmacstatPeripheral Status Registers Description Hpistat 1715 Pcistat Rmiirst Emac Configuration Register Emaccfg Description Emuctl Emulator Buffer Powerdown Register Emubufpd Description Pcieeai MACSEL1 MACSEL0 Device Status Register DescriptionEmifaen DDR2EN Pcien CFGGP2 CFGGP1 CFGGP0 Sysclkout MCBSP1EN PCI66 Lendian Bit Field Value DescriptionPcieeai MACSEL10 Variant Part Number Manufacturer LSB BOOTMODE30Jtag ID Jtagid Register Description Pullup/Pulldown Resistors Product Preview Configuration Examples Timers + Emac Gmii + Mdio System Interconnect Internal Buses, Bridges, and Switch Fabrics Data Switch Fabric Connections TMS320C6454 Switched Central Resource Block Diagram SCR Connection Matrix Configuration Switch Fabric C64x+ Megamodule SCR Connection Host Emac Priority Allocation ROM a Memory ArchitectureAET Sram TMS320C6454 L1P Memory Configurations TMS320C6454 L2 Memory Configurations AID0 Bit Memory ProtectionBandwidth Management Available Memory Page Protection Schemes Reset Type Megamodule Power-Down ControlMegamodule Resets Megamodule Reset Global or Local Revision Megamodule RevisionVersion Revision a Version Megamodule Interrupt Registers C64x+ Megamodule Register Descriptions Megamodule Idma Registers Megamodule Powerdown Control RegistersMegamodule Revision Register Megamodule Cache Configuration Registers MAR168 Controls Emifa CE2 Range A800 0000 A8FF Ffff Megamodule L1/L2 Memory Protection Registers L2MPPA6 L2MPPA3L2MPPA4 L2MPPA5 HEX Address Range Acronym Register Name Comments 11. Device Configuration Registers Chip-Level Registers10. CPU Megamodule Bandwidth Management Registers Cvdd Recommended Operating Conditions MIN NOM MAX Unit Recommended Operating Conditions TDO DVDD33 = MIN IOL = MAX Parameter Test Conditions MIN TYP MAX UnitOH = MAX II DC TDO Tester Pin Electronics 1 3.3-V Signal Transition Levels2 3.3-V Signal Transition Rates Parameter Information Timing Parameters and Board Routing Analysis Power-Supply Decoupling Recommended Clock and Control Signal Transition BehaviorPower Supplies Power-Supply Sequencing Product Preview EDMA3 Device-Specific Information Enhanced Direct Memory Access EDMA3 Controller Edma Binary Event Name Event Description Channel EDMA3 Channel Synchronization EventsC6454 EDMA3 Channel Synchronization Events1 EDMA3 Channel Controller Registers EDMA3 Peripheral Register DescriptionsC6454 EDMA3 Channel Synchronization Events DCHMAP35 DCHMAP32DCHMAP33 DCHMAP34 Emcrh EMREmrh Emcr Q1E0 Event Queue 1 Entry Register QSTAT3 QSTAT0QSTAT1 QSTAT2 EDMA3 Parameter RAM1 EDMA3 Transfer Controller 0 Registers EDMA3 Parameter RAM EDMA3 Transfer Controller 1 Registers EDMA3 Transfer Controller 2 Registers 109 EDMA3 Transfer Controller 3 Registers 111 Event Number Interrupt Event Interrupt Source InterruptsInterrupt Sources and Interrupt Controller 10. C6454 DSP Interrupts TINTHI1 TINTLO0TINTHI0 TINTLO1 Idmabuserr L2DMPAIdmacmpa NMI External Interrupts Electrical Data/Timing11. Timing Requirements for External Interrupts1 see Figure Type Initiator Reset ControllerPower-on Reset POR Pin 12. Reset Types Warm Reset Reset Pin CPU Reset System Reset Reset Type Status Register Description Reset PriorityReset Controller Register Parameter Reset Electrical Data/Timing14. Timing Requirements for Reset1 2 3see -8and Figure 720 1000 TMS320C6454 Power-Up Timing CLKIN1 CLKIN2 POR Resetstat PLL1 and PLL1 Controller Internal Clocks and Maximum Operating Frequencies 1 PLL1 Controller Device-Specific Information 1.2 PLL1 Controller Operating Modes 1.3 PLL1 Stabilization, Lock, and Reset TimesClock Signal MIN MAX Unit 16. PLL1 Clock Frequency Ranges MIN TYP 17. PLL1 Stabilization, Lock, and Reset Times18. PLL1 Controller Registers Including Reset Controller 2 PLL1 Controller Memory Map Pllpwrdn 3 PLL1 Controller Register Descriptions3.1 PLL1 Control Register Pllrst 20. PLL Multiplier Control Register Pllm Field Descriptions PLL Multiplier Control Register Ratio PLL Pre-Divider Control RegisterPreden D4EN PLL Controller Divider 4 Register D5EN PLL Controller Divider 5 Register Goset PLL Controller Command Register Gostat PLL Controller Status Register PLL Controller Clock Align Control Register SYS5 Plldiv Ratio Change Status RegisterSYS5 SYS4 SYS5ON SYS4ON SYS3ON SYS2ON Sysclk Status Register X1 Bypass X20, x25, x30 29. Timing Requirements for CLKIN1 Devices1 2 3 see Figure720 850 1000 PLL Modes Unit PLL2 and PLL2 Controller Pllref Pllen = 1 PLL2 Controller Device-Specific Information31. PLL2 Clock Frequency Ranges 1.2 PLL2 Controller Operating Modes HEX Address Range Acronym Description 2 PLL2 Controller Memory Map3 PLL2 Controller Register Descriptions 32. PLL2 Controller Registers D1EN PLL Controller Divider 1 Register PLL Controller Command Register ALN1 SYS1 SYS1ON 39. Timing Requirements for CLKIN21 2 3 see Figure 4 PLL2 Controller Input Clock Electrical Data/Timing 1 DDR2 Memory Controller Device-Specific Information DDR2 Memory Controller 40. DDR2 Memory Controller Registers 2 DDR2 Memory Controller Peripheral Register Descriptions3 DDR2 Memory Controller Electrical Data/Timing Emifa Device-Specific Information External Memory Interface a Emifa 41. Emifa Registers Emifa Peripheral Register Descriptions Aeclkin Emifa Electrical Data/Timing42. Timing Requirements for Aeclkin for EMIFA1 2 see Figure 720 850 1000UNIT 720Aeclkin AECLKOUT1 AAOE/ASOE a AAWE/ASWE a AR/W Aardy B Deasserted Setup = Hold =ACEx ABE70 ABA10 AED630 Read Data Aeclkout Aardya Asserted Deasserted Strobe Setup = Extended StrobeABA10 AED630 155 ASADS/ASREB AAOE/ASOEB AAWE/ASWEB BE1 BE2 BE3 BE4AEA190/ABA10 EA1 EA2 EA3 EA4 Write Latency = Hold Holda HOLD/HOLDA TimingHHOLDAL-HOLDL Hold time, Hold low after Holda low DSP Owns Bus Busreq Timing Delay time, Aeclkout high to Abusreq valid AECLKOUTx 11.1 I2C Device-Specific Information 11 I2C Peripheral I2CXSR I2COARSCL I2CCLKH I2CSAR 51. I2C Registers 11.2 I2C Peripheral Register Descriptions 11.3 I2C Electrical Data/Timing Standard Mode Fast Mode MIN MAX Unit MAX SDA SCLStop Start Repeated Start Stop Stop Start 54. HPI Control Registers Host-Port Interface HPI PeripheralHPI Device-Specific Information HPI Peripheral Register Descriptions HPI Electrical Data/Timing See -56through Figure HD150 HCS HasHCNTL10 HR/W Hhwil Hstrobea Hrdyb HR/W Hhwil Hstrobe a 46. HPI16 Write Timing has Not Used, Tied High 47. HPI16 Write Timing has Used HCS input HD310 output Hrdyb output Has input HCNTL10 input HR/W input 49. HPI32 Read Timing has Used Input HCS input 50. HPI32 Write Timing has Not Used, Tied High Input HCS input HD310 input 51. HPI32 Write Timing has Used Multichannel Buffered Serial Port McBSP McBSP Device-Specific Information 58. McBSP 1 Registers Product McBSP Electrical Data/Timing 181 Clks Clks ClkrClkx Clkx FSX Master Slave MIN MAXSlave MIN MAX Master Slave MIN Hold time, DR valid after Clkx high + 36P Setup time, DR valid before Clkx high 18P 186 Ethernet Bus Ethernet MAC Emac Interface Modes Emac Device-Specific Information Rmii 70. EMAC/MDIO Multiplexed Pins MII, RMII, and Gmii ModesBall Number Device PIN Name Interface Mode Clocking 71. Ethernet MAC Emac Control Registers Emac Peripheral Register Descriptions RX6FREEBUFFER MacconfigSoftreset RX5FREEBUFFER HEX Address Range Acronym 72. Emac Statistics Registers 02C8 2000 02C8 3FFF Emac Descriptor Memory 73. Emac Control Module Registers74. Emac Descriptor Memory Mtclk Emac Electrical Data/Timing MRXD3−MRXD0 Output 720 1000UNIT 1000 Mbps1000 Mbps 100/10 Mbps Mrclk Input MRXD7−MRXD4GMII only MTXD7−MTXD0 MTXD3−MTXD0NO.PARAMETER Rmrefclk Emac Rmii Electrical Data/Timing Mrxer Inputs 720 1000 Rmrefclk InputMRXD1-MRXD0 Mcrsdv Output Emac Rgmii Electrical Data/Timing 201 70. Emac Transmit Interface Timing Rgmii OperationAB Mdio Peripheral Register Descriptions 89. Mdio Registers Management Data Input/Output MdioMdio Device-Specific Information Mdio output Delay time, Mdclk low to Mdio data output valid 100Mdio input 92. Timer 0 Registers TimersTimers Device-Specific Information Timers Peripheral Register Descriptions TINPLx TOUTLx Timers Electrical Data/Timing94. Timing Requirements for Timer Inputs1 see Figure PCI Device-Specific Information 96. Default Values for PCI Configuration RegistersRegister Default Value Peripheral Component Interconnect PCI PCI Peripheral Register Descriptions 97. PCI Configuration Registers 98. PCI Back End Configuration Registers 99. DSP-toPCI Address Translation Registers HEX Address Offset Acronym Register Name 100. PCI Hook Configuration Registers101. PCI External Memory Space 4A7F Ffff 47FF Ffff48FF Ffff 49FF Ffff PCI Electrical Data/Timing 102. Gpio Registers General-Purpose Input/Output GpioGpio Device-Specific Information Gpio Peripheral Register Descriptions GPIx GPOx Gpio Electrical Data/Timing103. Timing Requirements for Gpio Inputs1 2 see Figure 105. Timing Requirements for Jtag Test Port see Figure Ieee 1149.1 JtagJtag Device-Specific Information Ieee 1149.1 Jtag Compatibility Statement AIR Flow Thermal Resistance Characteristics S-PBGA Package ZTZ/GTZThermal Data Packaging Information See ADDITIONS/MODIFICATIONS/DELETIONS Revision HistoryC6454 Revision History Changed -4title to EDMA3 Channel Controller Registers Product Preview Revision History 221 Qty Orderable Device Status PackageEco Plan MSL Peak TempPage Page Important Notice